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Code Activity
14379 commits 121 branches 59 tags 69 MiB
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Author SHA1 Message Date
Clifford Wolf
08ec33a5e5 Implemented simplemap support for "techmap -extern" 2014-08-02 21:55:13 +02:00
Clifford Wolf
bc947d4c7b Fixed a va_list corruption in logv_error() 2014-08-02 21:54:30 +02:00
Clifford Wolf
88cf00ce78 Be more conservative with printing decimal numbers in verilog backend 2014-08-02 21:54:02 +02:00
Clifford Wolf
ca1b5d50e0 Improved verilog output for ordinary $mux cells 2014-08-02 21:10:08 +02:00
Clifford Wolf
b6acbc82e6 Bugfix in "techmap -extern" 2014-08-02 20:54:30 +02:00
Clifford Wolf
8e7361f128 Removed at() method from RTLIL::IdString 2014-08-02 19:08:02 +02:00
Clifford Wolf
04727c7e0f No implicit conversion from IdString to anything else 2014-08-02 18:58:40 +02:00
Clifford Wolf
768eb846c4 More bugfixes related to new RTLIL::IdString 2014-08-02 18:14:21 +02:00
Clifford Wolf
08392aad8f Limit size of log_signal buffer to 100 elements 2014-08-02 15:52:21 +02:00
Clifford Wolf
e590ffc84d Improvements in new RTLIL::IdString implementation 2014-08-02 15:44:10 +02:00
Clifford Wolf
8fd1c269ac Fixed a performance bug in opt_reduce 2014-08-02 15:12:16 +02:00
Clifford Wolf
60f3dc9923 Implemented new reference counting RTLIL::IdString 2014-08-02 15:11:35 +02:00
Clifford Wolf
97ad0623df Fixed memory corruption related to id2cstr() 2014-08-02 13:34:07 +02:00
Clifford Wolf
b9bd22b8c8 More cleanups related to RTLIL::IdString usage 2014-08-02 13:19:57 +02:00
Clifford Wolf
14412e6c95 Preparations for RTLIL::IdString redesign: cleanup of existing code 2014-08-02 00:45:25 +02:00
Clifford Wolf
75ffd1643c Added logfile hash to statistics footer 2014-08-01 19:43:28 +02:00
Clifford Wolf
bd74ed7da4 Replaced sha1 implementation 2014-08-01 19:01:10 +02:00
Clifford Wolf
1e224506be Added per-pass cpu usage statistics 2014-08-01 18:42:10 +02:00
Clifford Wolf
d13eb7e099 Added ModIndex helper class, some changes to RTLIL::Monitor 2014-08-01 17:14:32 +02:00
Clifford Wolf
97a17d39e2 Packed SigBit::data and SigBit::offset in a union 2014-08-01 15:25:42 +02:00
Clifford Wolf
5e641acc90 Consolidated hana test benches into fewer files 
for pf in test_simulation_{always,and,buffer,decoder,inc,mux,nand,nor,or,seq,shifter,sop,techmap,xnor,xor}; do
gawk 'FNR == 1 { printf("\n// %s\n",FILENAME); } { gsub("^module *", sprintf("module f%d_",ARGIND)); print; }' \
    ${pf}_*_test.v > $pf.v; ../tools/autotest.sh $pf.v; mv -v ${pf}_*_test.v Attic/; done;

..etc..
 2014-08-01 03:57:37 +02:00
Clifford Wolf
03ef9a75c6 Added "test_autotb -n <num_iter>" option 2014-08-01 03:55:51 +02:00
Clifford Wolf
32a1cc3efd Renamed modwalker.h to modtools.h 2014-07-31 23:30:18 +02:00
Clifford Wolf
62c8a71525 Various cleanups in Makefile, Renamed default configurations 2014-07-31 23:14:17 +02:00
Clifford Wolf
069fe0db42 Added compiler + compiler version + compiler flags to version string 2014-07-31 23:07:00 +02:00
Clifford Wolf
c6fd82c70b Fixed build of verific bindings 2014-07-31 16:45:23 +02:00
Clifford Wolf
cdae8abe16 Renamed port access function on RTLIL::Cell, added param access functions 2014-07-31 16:38:54 +02:00
Clifford Wolf
b5a9e51b96 Added "trace" command 2014-07-31 15:02:16 +02:00
Clifford Wolf
cd9407404a Added RTLIL::Monitor 2014-07-31 14:45:14 +02:00
Clifford Wolf
e6d33513a5 Added module->design and cell->module, wire->module pointers 2014-07-31 14:11:39 +02:00
Clifford Wolf
1cb25c05b3 Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace 2014-07-31 13:19:47 +02:00
Clifford Wolf
1202f7aa4b Renamed "stdcells.v" to "techmap.v" 2014-07-31 02:32:00 +02:00
Clifford Wolf
6ca0c569d9 Added "techmap -assert" 2014-07-31 02:21:41 +02:00
Clifford Wolf
41555cde10 Reorganized stdcells.v (no actual code change, just moved and indented stuff) 2014-07-31 02:21:06 +02:00
Clifford Wolf
6166c76831 Added "yosys -A" 2014-07-31 01:05:27 +02:00
Clifford Wolf
e5c245df9d Added "yosys -Q" 2014-07-31 00:53:21 +02:00
Clifford Wolf
2541489105 Added techmap CONSTMAP feature 2014-07-30 22:04:30 +02:00
Clifford Wolf
7daad40ca4 Fixed counting verilog line numbers for "// synopsys translate_off" sections 2014-07-30 20:18:48 +02:00
Clifford Wolf
6400ae3648 Added write_file command 2014-07-30 19:59:29 +02:00
Clifford Wolf
7d98645fe8 Added "make -j{N}" support to "make test" 2014-07-30 19:23:26 +02:00
Clifford Wolf
ceecf5b153 Improvements in test_cell 2014-07-30 18:49:12 +02:00
Clifford Wolf
6c05badc43 New techmap default rules for $shr $sshr $shl $sshl 2014-07-30 18:49:12 +02:00
Clifford Wolf
3f0a5746ef Using native ezSAT shift ops in satgen, fixed $shift and $shiftx SAT models 2014-07-30 18:37:17 +02:00
Clifford Wolf
9b566a7efa Added native support for shift operations to ezSAT 2014-07-30 18:37:17 +02:00
Clifford Wolf
45fd26b76e Added "log_dump_val_worker(char *v)" 2014-07-30 15:58:21 +02:00
Clifford Wolf
e2a029b5d5 Added CodingStyle document 2014-07-30 14:10:49 +02:00
Clifford Wolf
a7c6b37abf Added "kernel/yosys.h" and "kernel/yosys.cc" 2014-07-30 14:10:15 +02:00
Clifford Wolf
273383692a Added "test_cell" command 2014-07-29 22:07:41 +02:00
Clifford Wolf
e6df25bf74 Renamed "write_autotest" to "test_autotb" and moved to passes/tests/ 2014-07-29 21:12:50 +02:00
Clifford Wolf
e605af8a49 Fixed Verilog pre-processor for files with no trailing newline 2014-07-29 20:14:25 +02:00