3 commits

Author	SHA1	Message	Date
Dan Ravensloft	85a14895ca	synth_intel: a10gx -> arria10gx	2019-12-10 13:48:10 +00:00
Larry Doolittle	50bcd9a728	Clean whitespace and permissions in techlibs/intel	2017-10-05 16:23:49 +02:00
dh73	cbaba62401	Adding Cyclone IV (E, GX), Arria 10, Cyclone V and LPM functions (ALTPLL and M9K); M9K is not finished yet. Achronix Speedster also in this commit. Both Arria10 and Speedster-i are still experimental due complexity, but you can experiment around those devices right now	2017-10-01 11:04:17 -05:00

Renamed from techlibs/altera_intel/max10/cells_map_max10.v (Browse further)