mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-11-11 08:32:04 +00:00
Code Activity
15779 commits 121 branches 60 tags 48 MiB
Commit graph

1 commit

Author SHA1 Message Date
Clifford Wolf
91dd87e60b Improved scope resolution of local regs in Verilog+AST frontend 2014-08-05 12:15:53 +02:00