yosys

15529 commits 121 branches 59 tags 45 MiB

Author	SHA1	Message	Date
Gary Wong	4ffd05af6f	verilog: add support for SystemVerilog string literals. Differences are new escape sequences (including escaped newline continuations and hex escapes) and triple-quoted literals.	2025-08-11 13:34:10 +02:00
Emil J. Tywoniak	36491569d2	Revert "verilog: add support for SystemVerilog string literals." This reverts commit `5feb1a1752`.	2025-08-11 13:34:10 +02:00
Krystine Sherwin	3959d19291	Reapply "Add groups to command reference" This reverts commit `81f87ce6ed`.	2025-08-06 13:52:12 +12:00
Krystine Sherwin	385d58562d	Docs: Move verilog.rst to using_yosys Was previously in yosys_internals which is more developer focused, rather than user focused.	2025-08-05 09:53:58 +12:00

Renamed from docs/source/yosys_internals/verilog.rst (Browse further)