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1501 commits 134 branches 66 tags 63 MiB
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3 commits

Author SHA1 Message Date
Clifford Wolf
e6d33513a5 Added module->design and cell->module, wire->module pointers 2014-07-31 14:11:39 +02:00
Clifford Wolf
10e5791c5e Refactoring: Renamed RTLIL::Design::modules to modules_ 2014-07-27 11:18:30 +02:00
Clifford Wolf
91eab69912 Added copy command 2014-02-06 22:09:21 +01:00