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Author SHA1 Message Date
whitequark
a0e658d412 cxxrtl: use cxxrtl_ prefix rather than cxxrtl. 
The former prefix does not need to be escaped in Verilog, unlike
the latter, and the Yosys convention is to use the former.
 2020-04-24 18:35:53 +00:00
Eddie Hung
4bfe6ebea9 bugpoint: skip ports with (* keep *) on; add header 2020-04-24 11:17:09 -07:00
Eddie Hung
ebd6fa945d tests: opt_expr update xnor/xor tests 2020-04-24 11:16:25 -07:00
Eddie Hung
83570bc0da opt_expr: more fixes for $xor/$xnor 2020-04-24 11:15:29 -07:00
Claire Wolf
3eb24809a1
Merge pull request #1995 from YosysHQ/eddie/fix_verific_wiretype 
verific: do not assert if wire not found; warn instead
 2020-04-24 14:09:47 +02:00
Dan Ravensloft
4ca5f9799b intel_alm: cleanup duplication 2020-04-24 11:26:48 +02:00
whitequark
f88378ae61 cxxrtl: improve printing of narrow memories. 2020-04-24 05:50:36 +00:00
whitequark
3738391bdd cxxrtl: fix handling of parametric modules with large parameters. 
These have a `$paramod$` prefix, not `$paramod\\`.
 2020-04-24 05:44:39 +00:00
Eddie Hung
90b71eb84b opt_expr: do not group by X, more fixes 2020-04-23 18:15:07 -07:00
Eddie Hung
d3555c667c verific: do not assert if wire not found; warn instead 2020-04-23 16:28:11 -07:00
Eddie Hung
b84415094c tests: add opt_expr tests 2020-04-23 15:58:36 -07:00
Eddie Hung
e7058593f4 opt_expr: improve single-bit $and/$or/$xor/$xnor cells; gate cells too 2020-04-23 15:57:48 -07:00
Eddie Hung
bf021a0e1f bugpoint: improve help text 2020-04-23 12:16:55 -07:00
Eddie Hung
b048afc3a6
Merge pull request #1974 from YosysHQ/eddie/abc9_disable_mfs 
abc9: tolerate &mfs failure by writing output file before calling it (and using that if it fails)
 2020-04-23 06:43:30 -07:00
Claire Wolf
dc9a72bc8d
Merge pull request #1989 from boqwxp/qbfsat_anyconst_sourcelocs 
qbfsat: Make hole name recovery from source locations more robust.
 2020-04-23 11:34:19 +02:00
Claire Wolf
1797c574da
Merge pull request #1988 from boqwxp/qbfsat 
qbfsat: Add `-assume-negative-polarity` option.
 2020-04-23 11:33:54 +02:00
Claire Wolf
ca31027fe1
Merge pull request #1986 from YosysHQ/eddie/verific_enum 
verific: import enum attributes from verific
 2020-04-23 11:28:05 +02:00
Dan Ravensloft
3d149aff73 intel_alm: work around a Quartus ICE 2020-04-23 11:03:28 +02:00
Alberto Gonzalez
4ee8452d34
qbfsat: Make hole name recovery more robust. Allow multiple cell types to share the same source location as long as only one $anyconst or $anyseq has that location. 2020-04-23 05:45:44 +00:00
Eddie Hung
b700592881
Merge pull request #1984 from YosysHQ/eddie/getParam_exception 
kernel: Cell::getParam() to throw exception again if not found
 2020-04-22 22:12:41 -07:00
Alberto Gonzalez
7369e6b26b
qbfsat: Add -assume-negative-polarity option. 2020-04-23 04:06:15 +00:00
Eddie Hung
51ae0f4e20 ecp5: ecp5_gsr to skip cells that don't have GSR parameter again 2020-04-22 17:53:08 -07:00
Eddie Hung
988d47af85 tests: read +/xilinx/cell_sim.v before xilinx_dsp test 2020-04-22 17:50:30 -07:00
Eddie Hung
592baebd22 xilinx: xilinx_dsp_cascade to check CREG for DSP48E1 only 2020-04-22 17:43:25 -07:00
Eddie Hung
5028e17f7d verific: import enum attributes from verific 2020-04-22 17:26:56 -07:00
Eddie Hung
db09e96dff test: ice40_dsp test to read +/ice40/cells_sim.v for default params 2020-04-22 16:35:35 -07:00
Eddie Hung
d2d90e4504 xilinx: improve xilinx_dffopt message 2020-04-22 16:25:23 -07:00
Eddie Hung
f582eb14af xilinx: xilinx_dffopt to read cells_sim.v; fix test 2020-04-22 16:25:23 -07:00
Eddie Hung
86ab7d3a6e kernel: Cell::getParam() to throw exception again if not found 
As it did before #1945
 2020-04-22 16:25:23 -07:00
Eddie Hung
fa9df06c9d
Merge pull request #1949 from YosysHQ/eddie/select_blackbox 
select: do not select inside black-/white- boxes unless '=' prefix used
 2020-04-22 15:35:05 -07:00
Eddie Hung
274098cce6
Merge pull request #1983 from YosysHQ/eddie/use_default_param 
Cleanup use of hard-coded default parameters in light of #1945
 2020-04-22 14:37:27 -07:00
whitequark
cf14e186eb
Merge pull request #1982 from AsuMagic/asu/cxxrtl-memory-queue-opt 
cxxrtl: keep the memory write queue sorted on insertion.
 2020-04-22 20:29:08 +00:00
Claire Wolf
beb9e4b299
Update passes/cmds/select.cc 
Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
 2020-04-22 21:31:32 +02:00
Eddie Hung
bf22cda912
Merge pull request #1969 from boqwxp/pool_emplace 
kernel: Add `pool` support for rvalue references and C++11 move semantics.
 2020-04-22 12:10:42 -07:00
Eddie Hung
7f33a0294b Cleanup use of hard-coded default parameters in light of #1945 2020-04-22 12:02:30 -07:00
Asu
dc77563a6a cxxrtl: keep the memory write queue sorted on insertion. 
Strategically inserting the pending memory write in memory::update to keep the
queue sorted allows us to skip the queue sort in memory::commit.

The Minerva SRAM SoC runs ~7% faster as a result.
 2020-04-22 20:53:12 +02:00
Eddie Hung
db27f2f378
Merge pull request #1973 from YosysHQ/eddie/fix1966 
tests: fix various/plugin.sh when PREFIX != /usr/local/share
 2020-04-22 10:19:30 -07:00
Eddie Hung
281cd10717 tests: update select black/white-box tests 2020-04-22 10:16:14 -07:00
Eddie Hung
eaa5a3e786 select: do not select black/white boxes by default, '=' prefix to do so 2020-04-22 10:15:56 -07:00
Eddie Hung
28623f19ee
Merge pull request #1950 from YosysHQ/eddie/design_import 
design: -import to not count black/white-boxes as candidates for top
 2020-04-22 09:32:13 -07:00
Eddie Hung
4f847cb64a yosys-config: spelling 2020-04-22 08:30:03 -07:00
Eddie Hung
634b5e2d9f tests: use yosys-config --datdir instead of hard-coded 2020-04-22 08:29:45 -07:00
Eddie Hung
a7c66fdc61 pool: add emplace() function 2020-04-22 08:14:07 -07:00
Claire Wolf
c32b4bded5
Merge pull request #1976 from YosysHQ/dave/fix-sim-const 
sim: Fix handling of constant-connected cell inputs at startup
 2020-04-22 16:57:34 +02:00
Claire Wolf
95c74b319b
Merge pull request #1979 from whitequark/cxxrtl-go-faster 
cxxrtl: Gas gas gas! I'm gonna step on the gas! Tonight I'll fly!
 2020-04-22 16:50:45 +02:00
Claire Wolf
9f1fb11b1d Clear current_scope when done with RTLIL generation, fixes #1837 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-04-22 14:51:20 +02:00
whitequark
93288b8eae cxxrtl: run edge detectors only once in eval(). 
As a result, Minerva SRAM SoC runs ~15% faster.
 2020-04-22 12:47:28 +00:00
whitequark
1d5b6ac253 cxxrtl: add an unsupported knob for manipulating clock trees. 
This is quite possibly the worst way to implement this, but it does
work for a subset of well-behaved designs, and can be used to measure
how much performance is lost simulating the inactive edge of a clock.

It should be replaced with a clock tree analyzer generating safe
code once it is clear how should such a thing look like.
 2020-04-22 01:15:27 +00:00
whitequark
5f17e0ced5 cxxrtl: use log_id() where appropriate. NFC. 2020-04-21 23:42:56 +00:00
Marcelina Kościelnicka
cd82afb740 bugpoint: Don't remove modules or cells while iterating over them. 
Reported by @ZirconiumX.
 2020-04-22 00:09:01 +02:00