Jannis Harder
0d30a4d479
rtlil: Add packed extract implementation for SigSpec
...
Previously `extract` on a `SigSpec` would always unpack it. Since a
significant amount of `SigSpec`s have one or few chunks, it's worth
having a dedicated implementation.
This is especially true, since the RTLIL frontend calls into this for
every `wire [lhs:rhs]` slice, making this `extract` take up 40% when
profiling `read_rtlil` with one of the largest coarse grained RTLIL
designs I had on hand.
With this change the `read_rtlil` profile looks like I would expect it
to look like, but I noticed that a lot of the other core RTLIL methods
also are a bit too eager with unpacking or implementing
`SigChunk`/`Const` overloads that just convert to a single chunk
`SigSpec` and forward to the implementation for that, when a direct
implementation would avoid temporary std::vector allocations. While not
relevant for `read_rtlil`, to me it looks like there might be a few easy
overall performance gains to be had by addressing this more generally.
2024-04-22 13:26:17 +02:00
Akash Levy
02f38c5df7
Merge branch 'YosysHQ:main' into master
2024-04-21 14:29:49 -07:00
Akash Levy
fa62642b70
Fix BOOST_PYTHON_LIB find
2024-04-19 21:56:11 -07:00
Martin Povišer
171577f909
Merge pull request #4340 from gadfort/abc-lib-merge
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add support for using ABCs library merging when providing multiple liberty files
2024-04-17 22:01:20 +02:00
akash
06ea0372ae
Updated Makefile
2024-04-17 11:19:15 -07:00
akash
04d30773bf
Need to add back in the removed boost python line
2024-04-17 07:21:45 -07:00
Akash Levy
7b12b2867c
Merge branch 'YosysHQ:main' into master
2024-04-17 05:34:30 -07:00
Akash Levy
d3d4077842
Use Preqorsor name so that generated files have correct header
2024-04-17 05:24:25 -07:00
github-actions[bot]
4897e89547
Bump version
2024-04-17 00:16:15 +00:00
Akash Levy
3945e6ecff
Merge branch 'YosysHQ:main' into master
2024-04-16 10:59:45 -07:00
Miodrag Milanović
52c04f3029
Merge pull request #4341 from YosysHQ/mmicko/ci_update
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Add new verific testing environment CI
2024-04-16 08:30:03 +02:00
Miodrag Milanovic
c38bbd7824
Add new verific testing environment CI
2024-04-16 07:50:50 +02:00
github-actions[bot]
40e8f5b69d
Bump version
2024-04-16 00:15:48 +00:00
Miodrag Milanović
e78c38b556
Merge pull request #4339 from YosysHQ/mmicko/lib_as_attribute
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verific: expose library name as module attribute
2024-04-15 20:25:49 +02:00
Jannis Harder
1527cc84c4
Merge pull request #4338 from jix/fix-formalff-setundef-srst
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formalff -setundef: Fix handling for has_srst FFs
2024-04-15 18:34:07 +02:00
Miodrag Milanovic
af94123730
verific: expose library name as module attribute
2024-04-15 17:01:07 +02:00
Jannis Harder
2bd889a59a
formalff -setundef: Fix handling for has_srst FFs
...
The `has_srst`` case was checking `sig_ce` instead of `sig_srst` due to
a copy and paste error.
This would crash when `has_ce` was false and could incorrectly determine
that an initial value is unused when `has_ce` and `has_srst` are both
set.
2024-04-15 11:53:30 +02:00
Miodrag Milanović
7bb2746208
Merge pull request #4334 from YosysHQ/docs_tidy
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Strip compilation date from doc outputs
2024-04-15 08:27:41 +02:00
Akash Levy
ee4605526c
Smallfix
2024-04-14 21:12:29 -07:00
Akash Levy
c841fb15b6
Updates for mac
2024-04-14 21:10:14 -07:00
Akash Levy
e398f8f4ad
Merge remote-tracking branch 'upstream/main'
2024-04-14 18:59:42 -07:00
Akash Levy
6a3bb58d5d
Updates from yosys
2024-04-14 18:53:44 -07:00
Krystine Sherwin
73d021562f
Docs: Rename source/temp to source/generated
2024-04-15 10:13:22 +12:00
Krystine Sherwin
953f5bbe6c
Docs: Remove end-before tag for yosys-abc
2024-04-15 09:50:46 +12:00
Martin Povišer
b827b9862f
Merge pull request #4265 from povik/iattr_help
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memory_map: Explain `-iattr` better
2024-04-13 18:13:58 +02:00
Martin Povišer
4a8cdfabbb
Merge pull request #4169 from povik/clean-opt_clean-step2
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opt_clean: Remove dead assertion
2024-04-13 18:12:40 +02:00
github-actions[bot]
ed46453cfc
Bump version
2024-04-13 00:14:07 +00:00
Krystine Sherwin
b3024289c6
Docs: Force read_verilog to avoid verific header
2024-04-13 11:33:04 +12:00
Krystine Sherwin
1d7b7ddfd7
Docs: Skip footer in logs
2024-04-13 11:29:11 +12:00
Krystine Sherwin
d4b6042e43
Makefile: Separate docs/usage stderr and stdout
2024-04-13 11:20:36 +12:00
Peter Gadfort
a48825a604
add support for using ABCs library merging when providing multiple liberty files
2024-04-12 13:57:29 -04:00
N. Engelhardt
e8ec19c273
add command that should not have any effect to hierarchy -generate test (this documents the current behavior, not sure if it is desired functionality)
2024-04-12 13:51:06 +02:00
N. Engelhardt
b87327d1b9
fix hierarchy -generate mode handling of cells
2024-04-12 13:38:33 +02:00
Miodrag Milanović
1c09862ad9
Merge pull request #4329 from YosysHQ/mmicko/codeowners_change
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Add workflows and CODEOWNERS and fixed gitignore
2024-04-12 10:46:37 +02:00
Miodrag Milanovic
0c7ac36dcf
Add workflows and CODEOWNERS and fixed gitignore
2024-04-11 14:56:00 +02:00
Akash Levy
45eee94a8f
Revert rpath strategy
2024-04-10 23:58:58 -07:00
github-actions[bot]
47bdb3e32f
Bump version
2024-04-11 00:16:34 +00:00
Emil J
c5912f4f95
Merge pull request #4313 from widlarizer/emil/fix-opt-demorgan-warning
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opt_demorgan: fix extra args warning
2024-04-10 12:49:14 +02:00
Miodrag Milanovic
e2cfcbcf25
fix .gitignore
2024-04-10 10:12:05 +02:00
Miodrag Milanovic
e01e942f81
Next dev cycle
2024-04-10 08:21:35 +02:00
Miodrag Milanovic
a1bb0255d6
Release version 0.40
2024-04-10 08:17:27 +02:00
akash
66b25d15c1
Update yosys for Docker
2024-04-09 13:06:39 -07:00
Akash Levy
930fdbd6a1
ORIGIN
2024-04-09 13:02:43 -07:00
N. Engelhardt
3d5e23e585
Merge pull request #4302 from YosysHQ/vhdl_2019
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Verific support for VHDL 2019
2024-04-09 18:25:05 +02:00
N. Engelhardt
18afa36acd
Merge pull request #4273 from YosysHQ/vhdl_params
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verific: Improve import VHDL constants
2024-04-09 18:01:41 +02:00
akash
dee5bb58c5
Update Makefile to allow for boost-python on CentOS 7
2024-04-09 07:56:18 -07:00
Akash Levy
29e9d3ea92
Updates for hiding verific
2024-04-09 07:16:22 -07:00
Akash Levy
0fa8098ff4
Updates for pyosys on Mac
2024-04-09 07:16:11 -07:00
Akash Levy
a8fe47ea50
Update gitignore and Makefile
2024-04-08 22:13:22 -07:00
Akash Levy
27f68db831
Merge branch 'YosysHQ:main' into master
2024-04-08 17:25:31 -07:00
