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Author SHA1 Message Date
Xiretza
9c31ecfab8 Makefile: don't bake DESTDIR into libyosys DT_SONAME 
DESTDIR is only used as a temporary destination for installed files
before they are packaged into an archive; the "real" installed location
is determined by PREFIX/{BIN,LIB,DAT}DIR.
 2021-07-05 16:39:16 +02:00
Xiretza
18f4ae482c Makefile: clean up PYOSYS configuration 2021-07-05 16:38:58 +02:00
Miodrag Milanovic
0dbb05a75e Add additional help 2021-07-05 09:16:54 +02:00
whitequark
862e84eb3d
Merge pull request #2842 from whitequark/fix-wasi-build 
Fix WASI build after commit 1d88bea1
 2021-06-19 12:10:29 +00:00
whitequark
02b4e67549 Fix WASI build after commit 1d88bea1. 2021-06-19 02:59:57 +00:00
Miodrag Milanović
5a73f296c9
Merge pull request #2836 from YosysHQ/gatecat/pyosys-sigint 
pyosys: Clear SIGINT handler after Python loads
 2021-06-18 12:07:50 +02:00
Rupert Swarbrick
e2c9580024 Move interface expansion in hierarchy.cc into a helper class 
There should be no functional change, but this splits up the control
flow across functions, using class fields to hold the state that's
being tracked. The result should be a bit easier to read.

This is part of work to add bind support, but I'm doing some
refactoring in the hierarchy pass to make the code a bit easier to
work with. The idea is that (eventually) the IFExpander object will
hold all the logic for expanding interfaces, and then other code can
do bind insertion.
 2021-06-16 21:48:18 -04:00
Zachary Snow
f2c2d73f36 sv: fix up end label checking 
- disallow [gen]blocks with an end label but not begin label
- check validity of module end label
- fix memory leak of package name and end label
- fix memory leak of module end label
 2021-06-16 21:48:05 -04:00
Ashton Snelgrove
092f0cb01e Include blif reader header in public facing extension header files. 2021-06-16 22:29:34 +02:00
gatecat
1d88bea18b pyosys: Clear SIGINT handler after Python loads 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-16 12:34:36 +01:00
Miodrag Milanovic
c0d8da20d5 Support command files in Verific 2021-06-16 11:21:44 +02:00
Xiretza
c6681508f1 verilog: fix leaking of type names in parser 2021-06-14 13:56:51 -04:00
Xiretza
b57e47fad8 verilog: fix wildcard port connections leaking memory 2021-06-14 13:56:51 -04:00
Xiretza
62a42c317c ast: delete wires and localparams after finishing const evaluation 2021-06-14 13:56:51 -04:00
Xiretza
091295a5a5 verilog: fix leaking ASTNodes 2021-06-14 13:56:51 -04:00
Xiretza
9ca5a91724 ast: fix error condition causing assert to fail 
type2str returns a string that doesn't start with $ or \, so it can't be
assigned to an IdString.
 2021-06-14 13:56:51 -04:00
Zachary Snow
b516c681fe macos: fix leak in proc_self_dirname() 2021-06-14 12:33:26 -04:00
Rupert Swarbrick
081111714e Simplify some RTLIL destructors 
No change in behaviour, but use range-based for loops instead of
iterators.
 2021-06-14 12:06:08 -04:00
Marcelina Kościelnicka
801ecc0e1d verilog: Squash a memory leak. 
That was added in ecc22f7fed
 2021-06-14 17:07:41 +02:00
Marcelina Kościelnicka
438bcc68c0 Add regression test for #2824. 2021-06-11 12:06:35 +01:00
gatecat
6a6d049f1c opt_muxtree: Update port_off and port_idx even for constant bits 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-11 12:06:35 +01:00
Marcelina Kościelnicka
1667ad658b opt_expr: Fix mul/div/mod by POT patterns to support >= 32 bits. 
The previous code, in addition to being needlessly limitted to 32 bits
in the first place, also had UB for the 31th bit (doing 1 << 31).
 2021-06-09 19:53:44 +02:00
Marcelina Kościelnicka
12b3a9765d opt_expr: Optimize div/mod by const 1. 
Turns out the code for div by a power of 2 is already almost capable of
optimizing this to a shift-by-0 or and-with-0, which will be further
folded into nothingness; let's beef it up to handle div by 1 as well.

Fixes #2820.
 2021-06-09 17:42:30 +02:00
Claire Xen
55e8f5061a
Merge pull request #2817 from YosysHQ/claire/fixemails 
Fixing old e-mail addresses and deadnames
 2021-06-09 13:22:52 +02:00
Claire Xenia Wolf
588137cd08 Fix deadname SVN links 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2021-06-09 12:44:37 +02:00
Claire Xenia Wolf
2d95a7da9c Intersynth URL 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2021-06-09 12:42:52 +02:00
Claire Xenia Wolf
0ff4fb1eb3 More deadname stuff 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2021-06-09 12:40:33 +02:00
Claire Xenia Wolf
06b99950ed Fix icestorm links 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2021-06-09 12:39:12 +02:00
Claire Xenia Wolf
a734face3a More deadname stuff 2021-06-09 12:33:41 +02:00
Claire Xenia Wolf
0ada13cbe2 Use HTTPS for website links, gatecat email 
git ls-tree -r --name-only HEAD | xargs sed -i -rf ~/fixemails.sed

s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi;
s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi;
s/((David)\s+)+(Shah|gatecat)\s+<(dave|david|gatecat)@(symbioticeda.com|yosyshq.com|ds0.me)>/gatecat <gatecat@ds0.me>/gi;
s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi;
s,https?://www.clifford.at/yosys/|http://yosyshq.net/yosys/,https://yosyshq.net/yosys/,g;
 2021-06-09 12:16:56 +02:00
Claire Xenia Wolf
92e705cb51 Fix files with CRLF line endings 2021-06-09 12:16:33 +02:00
Zachary Snow
2e697f5655 verilog: check for module scope identifiers during width detection 
The recent fix for case expression width detection causes the width of
the expressions to be queried before they are simplified. Because the
logic supporting module scope identifiers only existed in simplify,
looking them up would fail during width detection. This moves the logic
to a common helper used in both simplify() and detectSignWidthWorker().
 2021-06-08 15:03:16 -04:00
Zachary Snow
c79fbfe0a1 mem2reg: tolerate out of bounds constant accesses 
This brings the mem2reg behavior in line with the nomem2reg behavior.
 2021-06-08 15:02:57 -04:00
Zachary Snow
d9f11bb7a6 autoname: simple perf optimizations 2021-06-08 15:02:42 -04:00
Claire Xenia Wolf
72787f52fc Fixing old e-mail addresses and deadnames 
s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi;
s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi;
s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi;
s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi;
s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;
 2021-06-08 00:39:36 +02:00
Claire Xenia Wolf
e65ed3f228 Add claire deadname stuff to .mailmap 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2021-06-08 00:20:55 +02:00
Zachary Snow
8cfed1a979 sv: support tasks and functions within packages 2021-06-01 13:17:41 -04:00
Marcelina Kościelnicka
6d5d845788 kernel/mem: Recognize some deprecated memory port configs. 
Transparency is meaningless for asynchronous ports, so we assume
transparent == false to simplify the code in this case.  Likewise,
enable is meaningless, and we assume it is const-1.  However,
turns out that nMigen emits the former, and Verilog frontend emits
the latter, so squash these issues when ingesting a $memrd cell.

Fixes #2811.
 2021-06-01 03:18:02 +02:00
Marcelina Kościelnicka
13b901bf1c memory_map: Improve start_offset handling. 
Fixes #2775.
 2021-05-31 17:45:21 +02:00
Marcelina Kościelnicka
82f5829aba memory_share: Add read port merging. 
This is mostly meant for wide port recognition, but may also happen to
merge some ports with compatible initial/reset values (eg. 0 vs x).
 2021-05-29 16:05:58 +02:00
Marcelina Kościelnicka
2d10caabbc memory_share: Improve sat-based port sharing. 2021-05-28 14:25:33 +02:00
Marcelina Kościelnicka
cbf6b719fe Make a few passes auto-call Mem::narrow instead of rejecting wide ports. 
This essentially adds wide port support for free in passes that don't
have a usefully better way of handling wide ports than just breaking
them up to narrow ports, avoiding "please run memory_narrow" annoyance.
 2021-05-28 00:40:56 +02:00
Marcelina Kościelnicka
055ba748bc backends/verilog: Add support for memory read port reset and init value. 2021-05-27 23:47:42 +02:00
Marcelina Kościelnicka
aabe1c382e backends/verilog: Add wide port support. 2021-05-27 16:15:46 +02:00
Marcelina Kościelnicka
1eae6025e7 memory_share: Improve same-address merging, recognize wide write ports. 2021-05-27 15:53:12 +02:00
Marcelina Kościelnicka
b019db1f37 kernel/mem: Add helpers for write port widening. 2021-05-27 14:32:51 +02:00
Marcelina Kościelnicka
83a218141c kernel/mem: Add sub_addr helpers. 2021-05-26 03:34:02 +02:00
Marcelina Kościelnicka
57ca51be76 kernel/mem: Add prepare_wr_merge helper. 2021-05-26 02:55:00 +02:00
Marcelina Kościelnicka
64ba3c3842 backends/verilog: Try to preserve mem write port priorities. 2021-05-26 00:19:31 +02:00
Marcelina Kościelnicka
d99fce3bc7 mem/extract_rdff: Fix "no FF made" edge case. 
When converting a sync transparent read port with const address to async
read port, nothing at all needs to be done other than clk_enable change,
and thus we have no FF cell to return.  Handle this case correctly in
the helper and in its users.
 2021-05-25 23:42:31 +02:00