Miodrag Milanovic
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7fafaa896d
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do not require boost if pyosys is not used
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2019-08-22 11:57:46 -07:00 |
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Chris Shucksmith
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68e673d687
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require tcl-tk in Brewfile
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2019-08-22 11:57:25 -07:00 |
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Clifford Wolf
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5e0f6c9ae5
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Bump year in copyright notice
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-08-22 18:43:54 +02:00 |
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Miodrag Milanovic
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2b4e50ac3d
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Visual Studio build fix
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2019-08-02 17:08:59 +02:00 |
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Miodrag Milanovic
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2ec5a3ec92
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Fix linking issue for new mxe and pthread
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2019-08-02 16:55:14 +02:00 |
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Miodrag Milanovic
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ce0de937f4
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Fix yosys linking for mxe
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2019-08-02 16:55:14 +02:00 |
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Miodrag Milanovic
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bf59f31b43
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New mxe hacks needed to support 2ca237e
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2019-08-02 16:55:14 +02:00 |
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Miodrag Milanovic
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e9c5f1b346
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Fix formatting for msys2 mingw build using GetSize
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2019-08-02 16:55:14 +02:00 |
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David Shah
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82a2972068
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Update CHANGELOG
Signed-off-by: David Shah <dave@ds0.me>
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2019-07-26 16:45:51 +01:00 |
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Clifford Wolf
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1d58bbb79c
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Merge pull request #1175 from whitequark/write_verilog-fix-case-attr-position
write_verilog: fix placement of case attributes
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2019-07-09 22:19:34 +01:00 |
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David Shah
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c8979a3353
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Update CHANGELOG
Signed-off-by: David Shah <dave@ds0.me>
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2019-07-09 18:51:50 +01:00 |
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Clifford Wolf
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8af7ced5cd
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Merge pull request #1163 from whitequark/more-case-attrs
More support for case rule attributes
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2019-07-09 18:48:47 +01:00 |
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Clifford Wolf
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76f20492a4
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Merge pull request #1162 from whitequark/rtlil-case-attrs
Allow attributes on individual switch cases in RTLIL
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2019-07-09 18:48:38 +01:00 |
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Clifford Wolf
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17e0cc010c
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Merge pull request #1159 from btut/fix/1090_segfault_cell_and_wire
Throw runtime exception when trying to convert inexistend C++ object to Python
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2019-07-09 18:48:23 +01:00 |
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Clifford Wolf
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fecd3aa2b1
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Merge pull request #1147 from YosysHQ/clifford/fix1144
Improve specify dummy parser
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2019-07-09 18:47:08 +01:00 |
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Clifford Wolf
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d105e2f03f
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Merge pull request #1154 from whitequark/manual-sync-always
manual: explain the purpose of `sync always`
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2019-07-09 18:46:58 +01:00 |
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David Shah
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4b49c0201e
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Merge pull request #1153 from YosysHQ/dave/fix_multi_mux
memory_dff: Fix checking of feedback mux input when more than one mux
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2019-07-09 18:46:39 +01:00 |
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Clifford Wolf
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7b298479d4
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Fix read_verilog assert/assume/etc on default case label, fixes YosysHQ/SymbiYosys#53
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-07-09 18:46:28 +01:00 |
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Eddie Hung
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fc87c010c5
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autotest.sh to define _AUTOTB when test_autotb
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2019-07-09 18:46:18 +01:00 |
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Clifford Wolf
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ef0823690c
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Merge pull request #1146 from gsomlo/gls-test-abc-ext
tests: use optional ABCEXTERNAL when specified
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2019-07-09 18:44:57 +01:00 |
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Eddie Hung
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43069e9eb9
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Checkout yosys-0.9-rc branch of yosys-tests
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2019-07-02 10:06:56 -07:00 |
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Eddie Hung
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fdf0e82472
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Add missing CHANGELOG entries
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2019-06-28 11:16:53 -07:00 |
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Eddie Hung
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c4c39e9814
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Merge pull request #1139 from YosysHQ/dave/check-sim-iverilog
tests: Check that Icarus can parse arch sim models
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2019-06-27 12:31:15 -07:00 |
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Eddie Hung
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eab8384ec7
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Grr
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2019-06-27 11:53:42 -07:00 |
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Eddie Hung
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36f3cc9dcc
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Capitalisation
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2019-06-27 11:50:12 -07:00 |
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Eddie Hung
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d5cfe341f9
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Make CHANGELOG clearer
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2019-06-27 11:50:12 -07:00 |
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Eddie Hung
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6c210e5813
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Merge pull request #1143 from YosysHQ/clifford/fix1135
Add "pmux2shiftx -norange"
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2019-06-27 11:48:48 -07:00 |
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Eddie Hung
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ab7c431905
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Add simcells.v, simlib.v, and some output
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2019-06-27 11:13:49 -07:00 |
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Eddie Hung
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18acb72c05
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Add #1135 testcase
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2019-06-27 11:02:52 -07:00 |
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Eddie Hung
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760819e10d
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synth_xilinx -arch -> -family, consistent with older synth_intel
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2019-06-27 07:24:47 -07:00 |
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Eddie Hung
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ee77ee6973
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Merge pull request #1142 from YosysHQ/clifford/fix1132
Fix handling of partial covers in muxcover
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2019-06-27 07:21:31 -07:00 |
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Eddie Hung
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bb4ae8bc66
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Merge pull request #1138 from YosysHQ/koriakin/xc7nocarrymux
synth_xilinx: Add -nocarry and -nowidelut options
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2019-06-27 06:04:56 -07:00 |
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Eddie Hung
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3910bc2ea6
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Copy tests from eddie/fix1132
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2019-06-27 06:01:50 -07:00 |
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Clifford Wolf
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7c14678ec0
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Add "pmux2shiftx -norange", fixes #1135
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-06-27 10:59:12 +02:00 |
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Clifford Wolf
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69d810e4a8
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Fix handling of partial covers in muxcover, fixes #1132
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-06-27 09:42:58 +02:00 |
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Eddie Hung
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6db181471e
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Grrr
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2019-06-26 10:47:03 -07:00 |
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David Shah
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71b046d639
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tests: Check that Icarus can parse arch sim models
Signed-off-by: David Shah <dave@ds0.me>
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2019-06-26 18:46:22 +01:00 |
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Eddie Hung
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138989e1a3
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Fix spacing
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2019-06-26 10:09:18 -07:00 |
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Eddie Hung
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cb722e7b58
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Oops. Actually use nocarry flag as spotted by @koriakin
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2019-06-26 10:06:33 -07:00 |
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Clifford Wolf
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0d2b87e3ed
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Merge pull request #1137 from mmicko/cell_sim_fix
Simulation model verilog fix
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2019-06-26 19:06:10 +02:00 |
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Miodrag Milanovic
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ea0b6258ab
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Simulation model verilog fix
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2019-06-26 18:34:34 +02:00 |
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Eddie Hung
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4ce329aefd
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synth_ecp5 rename -nomux to -nowidelut, but preserve former
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2019-06-26 09:33:48 -07:00 |
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Eddie Hung
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7389b043c0
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Merge branch 'xc7nocarrymux' of https://github.com/koriakin/yosys into koriakin/xc7nocarrymux
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2019-06-26 09:33:38 -07:00 |
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Clifford Wolf
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0b7d648c6a
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Improve opt_clean handling of unused public wires
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-06-26 17:54:17 +02:00 |
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Clifford Wolf
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1b49380f6b
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Improve BTOR2 handling of undriven wires
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-06-26 17:42:00 +02:00 |
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Clifford Wolf
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f6053b8810
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Fix segfault on failed VERILOG_FRONTEND::const2ast, closes #1131
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-06-26 11:09:43 +02:00 |
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Clifford Wolf
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8e9ef891fe
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Do not clean up buffer cells with "keep" attribute, closes #1128
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-06-26 11:01:03 +02:00 |
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Clifford Wolf
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b3c36b4448
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Escape scope names starting with dollar sign in smtio.py
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-06-26 10:58:39 +02:00 |
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whitequark
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3d4102cfa4
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Add more ECP5 Diamond flip-flops.
This includes all I/O registers, and a few more regular FFs where it
was convenient.
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2019-06-26 01:57:29 +00:00 |
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Eddie Hung
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ab6e8ce0f0
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Add testcase from #335, fixed by #1130
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2019-06-25 08:43:58 -07:00 |
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