484 commits

Author	SHA1	Message	Date
Clifford Wolf	fc6dc0d7b8	Fixed handling of power operator	2013-11-07 22:20:00 +01:00
Clifford Wolf	d7cb62ac96	Fixed more extend vs. extend_u0 issues	2013-11-07 19:20:20 +01:00
Clifford Wolf	02f4f89fdb	Disabled const folding of ternary op when select is undef	2013-11-07 18:18:16 +01:00
Clifford Wolf	ed4bcd52e5	Fixed sign handling in constants	2013-11-07 14:53:10 +01:00
Clifford Wolf	83a8b8b5ca	Fixed const folding in corner cases with parameters	2013-11-07 14:08:53 +01:00
Clifford Wolf	536621a98b	Fixed at_zero evaluation of dynamic ranges	2013-11-07 11:25:19 +01:00
Clifford Wolf	f050c40519	Various fixes for correct parameter support	2013-11-07 10:02:11 +01:00
Clifford Wolf	f2786df146	Another fix for early width and sign detection in ast simplifier	2013-11-04 21:29:36 +01:00
Clifford Wolf	d38c67f53d	Fixed const folding of ternary operator	2013-11-04 16:46:14 +01:00
Clifford Wolf	8d226da694	Use proper bit width ans sign extension for const folding	2013-11-04 15:37:09 +01:00
Clifford Wolf	1325514d33	Fixes for early width and sign detection in ast simplifier	2013-11-04 08:28:13 +01:00
Clifford Wolf	472117d532	further improved early width and sign detection in ast simplifier	2013-11-04 06:04:42 +01:00
Clifford Wolf	ada80545fa	Behavior should be identical now to rev. 0b4a64ac6a (next: testing before constfold fixes)	2013-11-02 21:13:01 +01:00
Clifford Wolf	943329c1dc	Various ast changes for early expression width detection (prep for constfold fixes)	2013-11-02 13:00:17 +01:00
Clifford Wolf	23cf23418c	Fixed handling of boolean attributes (frontends)	2013-10-24 11:20:13 +02:00
Johann Glaser	6c4cbc03c2	Added support for notif0/notif1 primitives	2013-08-20 11:23:59 +02:00
Clifford Wolf	8656b1c08f	Added support for bufif0/bufif1 primitives	2013-08-19 19:50:04 +02:00
Clifford Wolf	4214561890	Improved ast dumping (ast/verilog frontend)	2013-08-19 19:49:14 +02:00
Clifford Wolf	56432a920f	Added defparam support to Verilog/AST frontend	2013-07-04 14:12:33 +02:00
Clifford Wolf	59dd02baa2	Fixes and improvements in AST const folding	2013-06-10 13:56:03 +02:00
Clifford Wolf	db98a18edb	Enabled AST/Verilog front-end optimizations per default	2013-06-10 13:19:04 +02:00
Clifford Wolf	c5ee2b306a	Merge branch 'bugfix'	2013-05-16 16:44:45 +02:00
Clifford Wolf	6cc8e848b6	Fixed synthesis of functions in latched blocks	2013-05-16 16:44:06 +02:00
Clifford Wolf	161565be10	Added AST_INITIAL (before verilog "initial" was mapped to AST_ALWAYS)	2013-03-31 11:19:11 +02:00
Clifford Wolf	7a99349de4	Improvements and bugfixes for generate blocks with local signals	2013-03-26 11:31:34 +01:00
Clifford Wolf	6a382f2aba	Fixed handling of unconditional generate blocks	2013-03-26 09:44:54 +01:00
Clifford Wolf	227520f94d	Added nosync attribute and some async reset related fixes	2013-03-25 17:13:14 +01:00
Clifford Wolf	df9753d398	Added mem2reg option to verilog frontend	2013-03-24 11:13:32 +01:00
Clifford Wolf	3a5244e913	Another fix in mem2reg ast simplify logic	2013-03-24 10:42:08 +01:00
Clifford Wolf	bb3357c027	Improved mem2reg handling in ast simplifier	2013-03-24 09:27:01 +01:00
Clifford Wolf	e45d1c8865	Tiny fixes to verilog parser	2013-03-23 18:54:31 +01:00
Clifford Wolf	a321a5c412	Moved stand-alone libs to libs/ directory and added libs/subcircuit	2013-02-27 09:32:19 +01:00
Clifford Wolf	4f0c2862a0	Added support for verilog genblock[index].member syntax	2013-02-26 13:18:22 +01:00
Clifford Wolf	7764d0ba1d	initial import	2013-01-05 11:13:26 +01:00