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656 commits

Author SHA1 Message Date
Jannis Harder
65145db7e7 rename: Add -witness mode 2022-08-16 13:37:30 +02:00
Jannis Harder
0cdb14df41 setundef: Do not add anyseq / anyconst to unused memory port clocks 
Instead set those unused clocks to zero.
 2022-08-16 13:37:30 +02:00
Jannis Harder
c0063288d6 Add the $anyinit cell and the formalff pass 
These can be used to protect undefined flip-flop initialization values
from optimizations that are not sound for formal verification and can
help mapping all solver-provided values in witness traces for flows that
use different backends simultaneously.
 2022-08-16 13:37:30 +02:00
N. Engelhardt
6f439dc59a
Merge pull request #3425 from YosysHQ/lofty/stat-json 2022-08-11 17:00:54 +02:00
Lofty
59facfa98c stat: add option for machine-readable json output 2022-08-11 13:41:01 +01:00
Lofty
a48dcd1d40 rename: add -scramble-name option to randomly rename selections 2022-08-08 16:03:28 +01:00
George Rennie
5dfad5101d chformal: Rename -coverprecond to -coverenable 2022-06-18 18:28:12 +01:00
Jannis Harder
e39c422734 chformal: Test -coverprecond and reuse the src attribute 2022-06-18 18:19:26 +01:00
George Rennie
c659bd1878 chformal: Add -coverprecond option 
This inserts $cover cells to cover the enable signal (precondition)
for the selected formal cells.
 2022-06-18 18:19:26 +01:00
N. Engelhardt
3eaa9e38e0
Merge pull request #3196 from bfg86/bfg86/rename 
Add -suffix option to rename -wire
 2022-06-13 16:00:04 +02:00
bfg86
aedd3b7999 Updating help-text with nakengelhardts suggestion. 2022-06-13 09:35:10 +02:00
N. Engelhardt
b8ede6162b
Merge pull request #3349 from nakengelhardt/select_count_scratchpad 
Make 'stat' and 'select -count' save counts to scratchpad
 2022-06-09 17:15:02 +02:00
Lofty
aae2c01326 sta: warn on unrecognised cells only once 2022-06-08 09:31:49 +01:00
Miodrag Milanovic
d88a5d26b7 Fix preventing show crashing with newer graphviz 2022-06-03 08:38:16 +02:00
N. Engelhardt
61b05051e1 also make 'stat' save counts to scratchpad 2022-06-01 16:01:07 +02:00
N. Engelhardt
a55c3db384 have 'select -count' save the count to scratchpad entry 'select.count' 2022-06-01 14:39:33 +02:00
Jannis Harder
fc65ea47df select: Fix -assert-none and -assert-any error output and docs 
Both of these options consider a selection containing only empty modules
as non-empty. This wasn't mentioned in the documentation nor did the
error message when using `select -assert-none` list those empty modules,
which produced a very confusing error message complaining about a
non-empty selection followed by an empty listing of the selection.

This fixes the documentation and changes the `-assert-none` and
`-assert-any` assertion error messages to also output fully selected
modules (this includes selected empty modules).

It doesn't change the messages for `-assert-count` etc. as they don't
count modules.
 2022-05-19 14:07:34 +02:00
Marcelina Kościelnicka
0aec79a0da show: Fix width labels. 
See #3266.
 2022-04-04 22:48:09 +02:00
Claire Xen
e016518866
Merge pull request #2019 from boqwxp/glift 
Add `glift` command for creating gate-level information flow tracking models and optimization problems
 2022-02-11 15:51:24 +01:00
bfg86
7ac98d1c87 Add -suffix option to rename -wire. 
See #3195
 2022-02-11 00:05:13 +01:00
Marcelina Kościelnicka
93508d58da Add $bmux and $demux cells. 2022-01-28 23:34:41 +01:00
Catherine
4f1d62d9b2 bugpoint: avoid infinite loop between -connections and -wires. 
Fixes #3113.
 2021-12-15 08:17:02 +00:00
Marcelina Kościelnicka
0aad88a2fb Add clean_zerowidth pass, use it for Verilog output. 
This should remove instances of zero-width sigspecs in the netlist,
avoiding problems in the Verilog backend with emitting them.

See #3103.
 2021-12-12 19:56:50 +01:00
Lofty
77327b2544 sta: very crude static timing analysis pass 
Co-authored-by: Eddie Hung <eddie@fpgeh.com>
 2021-11-25 17:20:27 +01:00
Marcelina Kościelnicka
107aad2cd2 show: Fix wire bit indexing. 
Fixes #3078.
 2021-11-12 15:09:58 +01:00
Marcelina Kościelnicka
e7d89e653c Hook up $aldff support in various passes. 2021-10-02 21:01:21 +02:00
Marcelina Kościelnicka
c58ac63c97 logger: Add -check-expected subcommand. 
This allows us to have multiple "expect this warning" calls in a single
long script, covering only as many passes as necessary.
 2021-08-12 17:41:39 +02:00
Marcelina Kościelnicka
fd79217763 Add v2 memory cells. 2021-08-11 13:34:10 +02:00
Marcelina Kościelnicka
009940f56c rtlil: Make Process handling more uniform with Cell and Wire. 
- add a backlink to module from Process
- make constructor and destructor protected, expose Module functions
  to add and remove processes
 2021-07-12 00:47:34 +02:00
Claire Xen
55e8f5061a
Merge pull request #2817 from YosysHQ/claire/fixemails 
Fixing old e-mail addresses and deadnames
 2021-06-09 13:22:52 +02:00
Zachary Snow
d9f11bb7a6 autoname: simple perf optimizations 2021-06-08 15:02:42 -04:00
Claire Xenia Wolf
72787f52fc Fixing old e-mail addresses and deadnames 
s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi;
s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi;
s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi;
s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi;
s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;
 2021-06-08 00:39:36 +02:00
Marcelina Kościelnicka
c4cc888b2c kernel/rtlil: Extract some helpers for checking memory cell types. 
There will soon be more (versioned) memory cells, so handle passes that
only care if a cell is memory-related by a simple helper call instead of
a hardcoded list.
 2021-05-22 21:43:00 +02:00
Marcelina Kościelnicka
a6081b46ce connect: Add -assert option, fix non-working sigmap. 
Should be useful for writing tests.
 2021-05-08 15:49:41 +02:00
Iris Johnson
4c39189b13
Clarify bugpoint documentation regarding output 
Bugpoint's current documentation does specify that the result of a run is stored as the current design,
however it's easy to skim over what that means in practice. 

Add a documentation comment to explain specifically that an after bugpoint `write_xyz` pass is required to save
the reduced design.
 2021-03-24 16:24:33 -05:00
Zachary Snow
c8b45a4a82 bugpoint: add runner option 2021-03-17 15:54:00 -04:00
gatecat
dd6d34f461 blackbox: Include whiteboxed modules 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-17 13:58:04 +00:00
Marcelina Kościelnicka
4e03865d5b Add support for memory writes in processes. 2021-03-08 20:16:29 +01:00
Dan Ravensloft
74dad5afe7 scc: Add -specify option to find loops in boxes 2021-01-26 16:23:08 +00:00
umarcor
e61b107072 plugin: enhance no-plugin error 2020-12-29 05:50:04 +01:00
whitequark
1838edf35c bugpoint: add -wires option. 2020-12-07 09:24:35 +00:00
whitequark
2b474a01e1 bugpoint: try to remove whole processes first. 2020-12-07 08:42:54 +00:00
whitequark
b1135a88dd bugpoint: accept quoted strings in -grep. 2020-12-07 08:42:54 +00:00
whitequark
75f9e9cb45 bugpoint: add -command option. 2020-12-07 08:42:54 +00:00
whitequark
d6a93b8b90 check: add support for processes. 2020-11-03 15:36:27 +00:00
whitequark
191406f930 check: reformat log/help text to match most other passes 2020-11-03 12:37:02 +00:00
N. Engelhardt
3238190797 use the new isPublic() in a few places 2020-09-14 12:43:18 +02:00
whitequark
00e7dec7f5 Replace "ILANG" with "RTLIL" everywhere. 
The only difference between "RTLIL" and "ILANG" is that the latter is
the text representation of the former, as opposed to the in-memory
graph representation. This distinction serves no purpose but confuses
people: it is not obvious that the ILANG backend writes RTLIL graphs.

Passes `write_ilang` and `read_ilang` are provided as aliases to
`write_rtlil` and `read_rtlil` for compatibility.
 2020-08-26 17:29:32 +00:00
Alberto Gonzalez
bbfa2d65fa
glift: Use ID() rather than string literals. 2020-07-01 19:51:48 +00:00
Alberto Gonzalez
eda1af73c4
glift: Use worker pattern. 2020-07-01 19:51:47 +00:00