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Code Activity
1868 commits 122 branches 59 tags 72 MiB
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87 commits

Author SHA1 Message Date
Clifford Wolf
48ca1ff9ef Improved ABC clock domain partitioning 2014-12-23 14:08:38 +01:00
Clifford Wolf
a216df0433 Added "abc -markgroups" 2014-12-23 12:29:02 +01:00
Clifford Wolf
76fa527492 Added support for multiple clock domains to "abc" pass 2014-12-21 16:52:05 +01:00
Clifford Wolf
25844b5683 Fixed "abc" pass for clk and enable signals driven by logic 2014-12-21 11:13:25 +01:00
Clifford Wolf
f7b323196f Added DFFE support to "abc" pass 2014-12-20 00:44:03 +01:00
Clifford Wolf
bb631c6f5c Also look for yosys-abc in parent dir on win32 2014-10-18 19:01:44 +02:00
William Speirs
31267a1ae8 Header changes so it will compile on VS 2014-10-17 11:41:36 +02:00
Clifford Wolf
0913e968f5 More win32/abc fixes 2014-10-12 14:48:19 +02:00
Clifford Wolf
0b9282a779 Added make_temp_{file,dir}() and remove_directory() APIs 2014-10-12 12:11:57 +02:00
Clifford Wolf
9b4d171e37 Using stringf() instead of asprintf() in "abc" pass 2014-10-12 11:17:53 +02:00
Clifford Wolf
b1596bc0e7 Added run_command() api to replace system() and popen() 2014-10-12 10:57:15 +02:00
Clifford Wolf
fea11f0fa4 Added API for generic cell cost calculations 2014-10-09 13:59:26 +02:00
Clifford Wolf
c3e779a65f Added $_BUF_ cell type 2014-10-03 10:12:28 +02:00
Clifford Wolf
f9a307a50b namespace Yosys 2014-09-27 16:17:53 +02:00
Clifford Wolf
5827826098 Small improvements in "abc" command handle_loops() function 2014-09-19 14:05:41 +02:00
Clifford Wolf
3aa003c8e9 Using "NOT" instead of "INV" as cell name in default abc genlib file 2014-09-19 13:15:31 +02:00
Clifford Wolf
f56b92818b Do not run "scorr" in "abc -fast" 2014-09-18 19:00:21 +02:00
Clifford Wolf
815fab9d71 Added "abc -fast" 2014-09-18 12:57:37 +02:00
Clifford Wolf
9ae559b990 Fixed $_NOR vs. $_NOR_ typo in abc.cc 2014-09-16 12:45:05 +02:00
Clifford Wolf
47c2637a96 Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $_OAI4_ 2014-08-16 18:29:39 +02:00
Clifford Wolf
b64b38eea2 Renamed $lut ports to follow A-Y naming scheme 2014-08-15 14:18:40 +02:00
Clifford Wolf
f092b50148 Renamed $_INV_ cell type to $_NOT_ 2014-08-15 14:11:40 +02:00
Clifford Wolf
1bf7a18fec Added module->ports 2014-08-14 16:22:52 +02:00
Clifford Wolf
996c06f64d Added "abc -D" for setting delay target 2014-08-14 11:05:25 +02:00
Clifford Wolf
28bc7aeb93 Filter ANSI escape sequences from ABC output 2014-08-13 13:40:29 +02:00
Clifford Wolf
04727c7e0f No implicit conversion from IdString to anything else 2014-08-02 18:58:40 +02:00
Clifford Wolf
14412e6c95 Preparations for RTLIL::IdString redesign: cleanup of existing code 2014-08-02 00:45:25 +02:00
Clifford Wolf
cdae8abe16 Renamed port access function on RTLIL::Cell, added param access functions 2014-07-31 16:38:54 +02:00
Clifford Wolf
e6d33513a5 Added module->design and cell->module, wire->module pointers 2014-07-31 14:11:39 +02:00
Clifford Wolf
1cb25c05b3 Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace 2014-07-31 13:19:47 +02:00
Clifford Wolf
7bd2d1064f Using log_assert() instead of assert() 2014-07-28 11:27:48 +02:00
Clifford Wolf
10e5791c5e Refactoring: Renamed RTLIL::Design::modules to modules_ 2014-07-27 11:18:30 +02:00
Clifford Wolf
4c4b602156 Refactoring: Renamed RTLIL::Module::cells to cells_ 2014-07-27 01:51:45 +02:00
Clifford Wolf
f9946232ad Refactoring: Renamed RTLIL::Module::wires to wires_ 2014-07-27 01:49:51 +02:00
Clifford Wolf
946ddff9ce Changed a lot of code to the new RTLIL::Wire constructors 2014-07-26 20:12:50 +02:00
Clifford Wolf
f8fdc47d33 Manual fixes for new cell connections API 2014-07-26 15:58:23 +02:00
Clifford Wolf
b7dda72302 Changed users of cell->connections_ to the new API (sed command) 
git grep -l 'connections_' | xargs sed -i -r -e '
	s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g;
	s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g;
	s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g;
	s/(->|\.)connections_.push_back/\1connect/g;
	s/(->|\.)connections_/\1connections()/g;'
 2014-07-26 15:58:23 +02:00
Clifford Wolf
cc4f10883b Renamed RTLIL::{Module,Cell}::connections to connections_ 2014-07-26 11:58:03 +02:00
Clifford Wolf
2bec47a404 Use only module->addCell() and module->remove() to create and delete cells 2014-07-25 17:56:19 +02:00
Clifford Wolf
6aa792c864 Replaced more old SigChunk programming patterns 2014-07-24 23:10:58 +02:00
Clifford Wolf
c094c53de8 Removed RTLIL::SigSpec::optimize() 2014-07-23 20:32:28 +02:00
Clifford Wolf
a62c21c9c6 Removed RTLIL::SigSpec::expand() method 2014-07-23 19:34:51 +02:00
Clifford Wolf
ec923652e2 Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3 2014-07-23 09:52:55 +02:00
Clifford Wolf
a8d3a68971 Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3 2014-07-23 09:49:43 +02:00
Clifford Wolf
260c19ec5a Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 1/3 2014-07-23 09:34:47 +02:00
Clifford Wolf
4b4048bc5f SigSpec refactoring: using the accessor functions everywhere 2014-07-22 20:39:37 +02:00
Clifford Wolf
a233762a81 SigSpec refactoring: renamed chunks and width to __chunks and __width 2014-07-22 20:39:37 +02:00
Siesh1oo
8127d5e8c3 - kernel/register.h, kernel/driver.cc: refactor rewrite_yosys_exe()/get_share_file_name() to portable proc_self_dirname()/proc_share_dirname(). 
This refactoring improves robustness and allows OSX support with only 7 new lines of code, and easy extension for other systems.
 - passes/abc/abc.cc, passes/cmds/show.cc, passes/techmap/techmap.cc: use new, refactored semantics.
 2014-03-12 23:17:14 +01:00
Clifford Wolf
91704a7853 Merged a few fixes for non-posix systems from github.com/Siesh1oo/yosys 
(see https://github.com/cliffordwolf/yosys/pull/28)
 2014-03-11 14:24:24 +01:00
Clifford Wolf
fa75c8286e Fixed memory corruption in passes/abc/blifparse.cc 2014-03-11 13:09:01 +01:00