mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-10-31 11:42:30 +00:00
Code Activity
12372 commits 122 branches 59 tags 73 MiB
Commit graph

12372 commits

This branch
This branch
All branches
Author SHA1 Message Date
Marcelina Kościelnicka
72d86c327e memory_dff: Recognize read ports with reset / initial value. 2021-08-11 14:17:48 +02:00
Marcelina Kościelnicka
24027b5446 proc_memwr: Use the v2 memwr cell. 2021-08-11 13:34:10 +02:00
Marcelina Kościelnicka
fd79217763 Add v2 memory cells. 2021-08-11 13:34:10 +02:00
github-actions[bot]
b96eb888cc Bump version 2021-08-11 00:52:20 +00:00
Marcelina Kościelnicka
e6f3d1c225 kernel/mem: Introduce transparency masks. 2021-08-11 00:04:16 +02:00
Michael Singer
681a1c07e5 Allow optional comma after last entry in enum 2021-08-09 22:25:57 -06:00
github-actions[bot]
f368e2c7e6 Bump version 2021-08-10 00:52:49 +00:00
Marcelina Kościelnicka
d25b9088c8 Refactor common parts of SAT-using optimizations into a helper. 
This also aligns the functionality:

- in all cases, the onehot attribute is used to create appropriate
  constraints (previously, opt_dff didn't do it at all, and share
  created one-hot constraints based on $pmux presence alone, which
  is unsound)
- in all cases, shift and mul/div/pow cells are now skipped when
  importing the SAT problem (previously only memory_share did this)
  — this avoids creating clauses for hard cells that are unlikely
  to help with proving the UNSATness needed for optimization
 2021-08-09 16:54:35 +02:00
github-actions[bot]
d8fcf1ab25 Bump version 2021-08-08 00:50:48 +00:00
Marcelina Kościelnicka
98003430d6 opt_merge: Use FfInitVals. 
Partial #2920 fix.
 2021-08-08 01:19:22 +02:00
github-actions[bot]
a24906a7d2 Bump version 2021-08-07 00:45:55 +00:00
Marcelina Kościelnicka
52cbf1bea5 verilog: Support tri/triand/trior wire types. 
These are, by the standard, just aliases for wire/wand/wor.

Fixes #2918.
 2021-08-06 21:35:43 +02:00
github-actions[bot]
2e421feb0e Bump version 2021-08-05 00:51:08 +00:00
Marcelina Kościelnicka
63f9e0544f memory_share: Don't skip ports with EN wired to input for SAT sharing. 
Fixes #2912.
 2021-08-04 04:47:43 +02:00
github-actions[bot]
d8b0c3277f Bump version 2021-08-04 00:49:53 +00:00
Marcelina Kościelnicka
8733e1923a memory_bram: Move init data swizzling before other swizzling. 
Fixes #2907.
 2021-08-03 15:04:10 +02:00
github-actions[bot]
ca8ad62696 Bump version 2021-08-03 00:55:22 +00:00
Miodrag Milanovic
be04d8834e Require latest verific 2021-08-02 10:29:58 +02:00
github-actions[bot]
10bcc4e192 Bump version 2021-08-02 00:50:24 +00:00
Marcelina Kościelnicka
ec2a468bd3 backend/verilog: Add alternate mode for transparent read port output. 
This mode will be used whenever read port cannot be handled in the
"extract address register" way, ie. whenever it has enable, reset,
init functionality or (in the future) mixed transparency mask.
 2021-08-01 19:11:29 +02:00
Marcelina Kościelnicka
4451f7f5e9 memory_bram: Some refactoring 
This will make more sense when the new transparency masks land.

Fixes #2902.
 2021-08-01 16:51:24 +02:00
github-actions[bot]
12db9b4273 Bump version 2021-07-31 00:50:30 +00:00
Miodrag Milanović
c4a295cb8d
Update version.yml 2021-07-30 19:50:02 +02:00
Maciej Dudek
cfddef5d7d Fixes xc7 BRAM36s 
UG473 from Xilinx states that 15 bit should always be set if RAMB isn't in cascade mode.

Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
 2021-07-30 16:17:22 +02:00
Zachary Snow
c016f6a423 proc_rmdead: use explicit pattern set when there are no wildcards 
If width of a case expression was large, explicit patterns could cause
the existing logic to take an extremely long time, or exhaust the
maximum size of the underlying set. For cases where all of the patterns
are fully defined and there are no constants in the case expression,
this change uses a simple set to track which patterns have been seen.
 2021-07-29 20:55:59 -04:00
Zachary Snow
4fec3a85cd genrtlil: add width detection for AST_PREFIX nodes 2021-07-29 20:55:31 -04:00
github-actions[bot]
87ef1dd805 Bump version 2021-07-30 00:52:33 +00:00
Marcelina Kościelnicka
54e75129e5 opt_lut: Allow more than one -dlogic per cell type. 
Fixes #2061.
 2021-07-29 17:30:07 +02:00
Zachary Snow
3156226233 verilog: save and restore overwritten macro arguments 2021-07-28 21:52:16 -04:00
github-actions[bot]
a055145b95 Bump version 2021-07-29 00:49:14 +00:00
Marcelina Kościelnicka
8bdc019730 verilog: Emit $meminit_v2 cell. 
Fixes #2447.
 2021-07-28 23:18:38 +02:00
Marcelina Kościelnicka
e9effd58d2 backends/verilog: Support meminit with mask. 2021-07-28 23:18:38 +02:00
Marcelina Kościelnicka
19720b970d memory: Introduce $meminit_v2 cell, with EN input. 2021-07-28 23:18:38 +02:00
github-actions[bot]
37d76deef1 Bump version 2021-07-28 00:52:46 +00:00
Marcelina Kościelnicka
a0e912ba99 proc: Run opt_expr at the end 2021-07-27 20:44:45 +02:00
Marcelina Kościelnicka
436d42c00c opt_expr: Propagate constants to port connections. 
This adds one simple piece of functionality to opt_expr: when a cell
port is connected to a fully-constant signal (as determined by sigmap),
the port is reconnected directly to the constant value.  This is just
enough optimization to fix the "non-constant $meminit input" problem
without requiring a full opt_clean or a separate pass.
 2021-07-27 20:44:26 +02:00
github-actions[bot]
9600f20be8 Bump version 2021-07-27 00:52:14 +00:00
Miodrag Milanovic
45968ad740 Add version bump workflow 2021-07-26 11:25:32 +02:00
Miodrag Milanovic
987fca5297 Update to latest verific 2021-07-21 09:46:53 +02:00
Rupert Swarbrick
7a25246a7e Use new read_id_num helper function elsewhere in hierarchy.cc 2021-07-20 10:13:15 -04:00
Rupert Swarbrick
8fd6b45a3c Extract connection checking logic from expand_module in hierarchy.cc 
No functional change, but pulls more logic out of the expand_module
function.
 2021-07-20 10:13:15 -04:00
whitequark
a04844bdf8
Merge pull request #2885 from whitequark/cxxrtl-fix-2883 
cxxrtl: treat wires with multiple defs as not inlinable
 2021-07-20 13:12:11 +00:00
whitequark
72beee2ccc
Merge pull request #2884 from whitequark/cxxrtl-fix-2882 
cxxrtl: treat assignable internal wires used only for debug as locals
 2021-07-20 13:12:03 +00:00
whitequark
1a6ddf7892 cxxrtl: treat wires with multiple defs as not inlinable. 
Fixes #2883.
 2021-07-20 10:30:39 +00:00
whitequark
225af830c1 cxxrtl: treat assignable internal wires used only for debug as locals. 
This issue was introduced in commit 4aa65f40 while fixing #2739.

Fixes #2882.
 2021-07-20 10:10:42 +00:00
whitequark
c2afcbe78d
Merge pull request #2881 from whitequark/cxxrtl-sideways-colon 
cxxrtl: escape colon in variable names in VCD writer
 2021-07-20 09:30:08 +00:00
whitequark
fc84f23001 cxxrtl: escape colon in variable names in VCD writer. 
The following VCD file crashes GTKWave's VCD loader:

    $var wire 1 ! x:1 $end
    $enddefinitions $end

In practice, a colon can be a part of a variable name that is
translated from a Verilog function, something like:

    update$func$.../hdl/hazard3_csr.v:350$2534.$result
 2021-07-19 16:22:55 +00:00
whitequark
9af88951bc
Merge pull request #2880 from whitequark/cxxrtl-fix-2877 
cxxrtl: add debug_item::{get,set}
 2021-07-18 07:35:23 +00:00
whitequark
948fc10d7b cxxrtl: add debug_item::{get,set}. 
Fixes #2877.
 2021-07-18 06:20:45 +00:00
whitequark
101d72ccb3
Merge pull request #2879 from whitequark/cxxrtl-fix-2739-again 
cxxrtl: treat internal wires used only for debug as constants
 2021-07-17 17:22:15 +00:00