mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-12-23 04:33:46 +00:00
Code Activity
1215 commits 114 branches 62 tags 60 MiB
Commit graph

2 commits

Author SHA1 Message Date
Clifford Wolf
d4a1b0af5b Added support for dlatchsr cells 2014-03-31 14:14:40 +02:00
Clifford Wolf
1afe6589df Renamed stdcells_sim.v to simcells.v and fixed blackbox.v 2013-11-24 20:44:00 +01:00
Renamed from techlibs/common/stdcells_sim.v (Browse further)