Robert O'Callahan
c7df6954b9
Remove .c_str() from stringf parameters
2025-09-01 23:34:42 +00:00
Lofty
8cc9aa7fc6
intel_alm: drop quartus support
2024-05-03 11:32:33 +01:00
KrystalDelusion
9465b2af95
Fitting help messages to 80 character width
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Uses the regex below to search (using vscode):
^\t\tlog\("(.{10,}(?<!\\n)|.{81,}\\n)"\);
Finds any log messages double indented (which help messages are)
and checks if *either* there are is no newline character at the end,
*or* the number of characters before the newline is more than 80.
2022-08-24 10:40:57 +12:00
Lofty
9f7a55c99f
intel_alm: M10K write-enable is negative-true
2022-03-09 20:18:06 +00:00
Lofty
a31c8a82be
intel_alm: preliminary Arria V support
2021-11-25 17:20:36 +01:00
Claire Xenia Wolf
72787f52fc
Fixing old e-mail addresses and deadnames
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s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi;
s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi;
s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi;
s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi;
s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g ;
2021-06-08 00:39:36 +02:00
gatecat
eb106732d9
intel_alm: Add global buffer insertion
...
Signed-off-by: gatecat <gatecat@ds0.me>
2021-05-15 22:37:06 +01:00
gatecat
5dba138c87
intel_alm: Add IO buffer insertion
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-05-15 22:37:06 +01:00
gatecat
cae905f551
Blackbox all whiteboxes after synthesis
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This prevents issues like processes in whiteboxes triggering an error in
the JSON backend.
Signed-off-by: gatecat <gatecat@ds0.me>
2021-03-17 21:07:20 +00:00
Dan Ravensloft
028f96e536
intel_alm: better map wide but shallow multiplies
2020-08-28 23:44:16 +02:00
Dan Ravensloft
1a07b330f8
intel_alm: Add multiply signedness to cells
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Quartus assumes unsigned multiplication by default, breaking signed
multiplies, so add an input signedness parameter to the MISTRAL_MUL*
cells to propagate to Quartus' <family>_mac cells.
2020-08-26 22:50:16 +02:00
Dan Ravensloft
034b9ec716
intel: move Cyclone V support to intel_alm
2020-08-20 18:25:05 +02:00
Marcelina Kościelnicka
9a4f420b4b
Replace opt_rmdff with opt_dff.
2020-08-07 13:21:03 +02:00
Dan Ravensloft
a2fb84fd0c
intel_alm: direct M10K instantiation
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This reverts commit a3a90f6377
2020-07-27 15:39:06 +02:00
Dan Ravensloft
62311b7ec0
intel_alm: increase abc9 -W
2020-07-26 23:56:54 +02:00
Lofty
a3a90f6377
Revert "intel_alm: direct M10K instantiation"
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This reverts commit 09ecb9b2cf
2020-07-13 18:05:38 +02:00
Dan Ravensloft
09ecb9b2cf
intel_alm: direct M10K instantiation
2020-07-05 23:28:59 +02:00
Dan Ravensloft
b004f09018
intel_alm: DSP inference
2020-07-05 05:39:20 +02:00
Marcelina Kościelnicka
3ca2de0f77
synth_intel_alm: Use dfflegalize.
2020-07-04 22:56:16 +02:00
Eddie Hung
3db3e1e149
intel_alm: add $__ prefix to MISTRAL_FF_SYNCONLY
2020-07-04 19:45:10 +02:00
Dan Ravensloft
83cde2d02b
intel_alm: ABC9 sequential optimisations
2020-07-04 19:45:10 +02:00
whitequark
7191dd16f9
Use C++11 final/override keywords.
2020-06-18 23:34:52 +00:00
Dan Ravensloft
8b4eb78849
intel_alm: fix DFFE matching
2020-06-11 19:55:51 +02:00
Eddie Hung
8fbb55f4ab
synth_*: no need to explicitly read +/abc9_model.v
2020-05-14 10:33:56 -07:00
Dan Ravensloft
5b779f7f4e
intel_alm: direct LUTRAM cell instantiation
...
By instantiating the LUTRAM cell directly, we avoid a trip through
altsyncram, which speeds up Quartus synthesis time. This also gives
a little more flexibility, as Yosys can build RAMs out of individual
32x1 LUTRAM cells.
While working on this, I discovered that the mem_init0 parameter of
<family>_mlab_cell gets ignored by Quartus.
2020-05-07 21:03:13 +02:00
Dan Ravensloft
4ca5f9799b
intel_alm: cleanup duplication
2020-04-24 11:26:48 +02:00
Dan Ravensloft
3d149aff73
intel_alm: work around a Quartus ICE
2020-04-23 11:03:28 +02:00
Dan Ravensloft
43cc6bd8a1
synth_intel_alm: VQM support
2020-04-15 16:15:25 +02:00
Dan Ravensloft
2e37e62e6b
synth_intel_alm: alternative synthesis for Intel FPGAs
...
By operating at a layer of abstraction over the rather clumsy Intel primitives,
we can avoid special hacks like `dffinit -highlow` in favour of simple techmapping.
This also makes the primitives much easier to manipulate, and more descriptive
(no more cyclonev_lcell_comb to mean anything from a LUT2 to a LUT6).
2020-04-15 11:40:41 +02:00
