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Author SHA1 Message Date
Miodrag Milanovic
0d31aa6008 Proper std::move 2022-05-27 11:04:16 +02:00
Miodrag Milanovic
7ee570a75e Use proper operator 2022-05-27 10:23:34 +02:00
Miodrag Milanović
b0c71ed594
Merge pull request #3053 from DanielHuisman/pr-2 
Fix emcc warnings for WebAssembly build
 2022-05-27 10:13:44 +02:00
github-actions[bot]
f698a0514d Bump version 2022-05-26 00:17:28 +00:00
Jannis Harder
b75fa62e9b verilog: fix $past's signedness 2022-05-25 16:32:08 -04:00
Miodrag Milanović
63c9c9be5c
Merge pull request #3011 from DanielHuisman/pr-1 
Update WaveDrom script URLs in YosysJS demo
 2022-05-25 17:34:19 +02:00
Jannis Harder
8e9471c695
Merge pull request #3335 from programmerjake/divfloor-in-write_smt2 
add $divfloor support to write_smt2
 2022-05-25 12:25:04 +02:00
Miodrag Milanović
904e2efe11
Merge pull request #3138 from DanielG/fix-git-rev 
Make GIT_REV logic work in release tarballs
 2022-05-25 11:33:11 +02:00
Daniel Gröber
222e7a2da3 Make GIT_REV logic work in release tarballs 
Currently GIT_REV doesn't get set properly when building a release
tarball. To fix this we arrange for .gitcommit to contain the (short)
commit hash in tarballs generated with git-archive(1) using export-subst in
gitattributes. This way the correct commit hash is (reproducibly) included
in the release tarballs while not burdening the maintainers with updating
it in the git repo.

Please note this even works on Github and similar forges as they use
git-archive for generating tarballs so this works out quite nicely.
 2022-05-25 11:20:09 +02:00
Jannis Harder
cffec1f95f verilog: fix signedness when removing unreachable cases 2022-05-24 23:03:31 -04:00
Jacob Lifshay
d53479a0d6 add $divfloor support to write_smt2 
Fixes: #3330
 2022-05-24 01:34:25 -07:00
github-actions[bot]
c525b5f919 Bump version 2022-05-24 00:18:18 +00:00
Miodrag Milanović
335b4888ce
Merge pull request #3332 from YosysHQ/verific_f 
Update Verific command file documentation
 2022-05-23 20:01:44 +02:00
Miodrag Milanovic
fdb393b6ce fix text to fit 80 columns 2022-05-23 19:57:21 +02:00
Miodrag Milanovic
4a5790d404 Update verific command file documentation 2022-05-23 19:35:14 +02:00
Miodrag Milanovic
a6ec5754c6 Use analysis mode if set in file 2022-05-23 19:13:45 +02:00
Miodrag Milanović
e47cfe277e
Merge pull request #3331 from YosysHQ/git_rev_fix 
work around the new(ish) git safe.directory restrictions
 2022-05-23 18:33:11 +02:00
Jannis Harder
87149b3f8e Change way to get commit sha 2022-05-23 17:07:17 +02:00
gatecat
166a175983 abc9_ops: Don't leave unused derived modules lying around 
These later become accidentally used for techmap replacements for
blackboxes that we don't actually want.

Signed-off-by: gatecat <gatecat@ds0.me>
 2022-05-23 15:02:25 +01:00
github-actions[bot]
0b1a1a576b Bump version 2022-05-21 00:16:34 +00:00
Jannis Harder
795c445159
Merge pull request #3324 from jix/confusing-select-errors 
select: Fix -assert-none and -assert-any error output and docs
 2022-05-20 17:40:40 +02:00
Jannis Harder
fc65ea47df select: Fix -assert-none and -assert-any error output and docs 
Both of these options consider a selection containing only empty modules
as non-empty. This wasn't mentioned in the documentation nor did the
error message when using `select -assert-none` list those empty modules,
which produced a very confusing error message complaining about a
non-empty selection followed by an empty listing of the selection.

This fixes the documentation and changes the `-assert-none` and
`-assert-any` assertion error messages to also output fully selected
modules (this includes selected empty modules).

It doesn't change the messages for `-assert-count` etc. as they don't
count modules.
 2022-05-19 14:07:34 +02:00
github-actions[bot]
015ca4ddac Bump version 2022-05-19 00:17:59 +00:00
Marcelina Kościelnicka
606f1637ae Add memory_bmux2rom pass. 2022-05-18 22:48:55 +02:00
Marcelina Kościelnicka
982a11c709 Add memory_libmap tests. 2022-05-18 17:32:56 +02:00
Marcelina Kościelnicka
2a2dc12eb6 gatemate: Use memory_libmap pass. 2022-05-18 17:32:56 +02:00
Marcelina Kościelnicka
2dcb0797f0 machxo2: Use memory_libmap pass. 2022-05-18 17:32:56 +02:00
Marcelina Kościelnicka
9d11575856 efinix: Use memory_libmap pass. 2022-05-18 17:32:56 +02:00
Marcelina Kościelnicka
f4d1426229 anlogic: Use memory_libmap pass. 2022-05-18 17:32:56 +02:00
Marcelina Kościelnicka
d7dc2313b9 ice40: Use memory_libmap pass. 2022-05-18 17:32:56 +02:00
Marcelina Kościelnicka
3b2f95953c xilinx: Use memory_libmap pass. 2022-05-18 17:32:56 +02:00
Marcelina Kościelnicka
e4d811561c gowin: Use memory_libmap pass. 2022-05-18 17:32:56 +02:00
Marcelina Kościelnicka
0a8eaca322 nexus: Use memory_libmap pass. 2022-05-18 17:32:56 +02:00
Marcelina Kościelnicka
a04b025abf ecp5: Use memory_libmap pass. 2022-05-18 17:32:56 +02:00
Marcelina Kościelnicka
7c5dba8b77 Add memory_libmap pass. 2022-05-18 17:32:56 +02:00
Marcelina Kościelnicka
9450f308f0 proc_rom: Add special handling of const-0 address bits. 2022-05-18 17:32:30 +02:00
github-actions[bot]
06ef3f264a Bump version 2022-05-18 00:16:27 +00:00
Miodrag Milanović
7c64c70727
Merge pull request #3310 from robinsonb5-PRs/master 
Now calls Tcl_Init after creating the interp, fixes clock format.
 2022-05-17 09:33:20 +02:00
Marcelina Kościelnicka
98c7804b89 opt_ffinv: Use ModIndex instead of ModWalker. 
This avoids using out-of-data index information.
 2022-05-17 02:52:21 +02:00
Alastair M. Robinson
6c6017c973 Use log_warning when Tcl_Init fails, report error with Tcl_ErrnoMsg. 2022-05-16 20:22:28 +01:00
Jannis Harder
2864f2826a
Merge pull request #3314 from jix/sva_value_change_logic_wide 
verific: Use new value change logic also for $stable of wide signals.
 2022-05-16 16:15:04 +02:00
github-actions[bot]
3f8fb28cd2 Bump version 2022-05-14 00:19:50 +00:00
Marcelina Kościelnicka
2858bb03cd Add opt_ffinv pass. 2022-05-13 23:02:30 +02:00
github-actions[bot]
f56a3bd48f Bump version 2022-05-13 00:19:56 +00:00
Marcelina Kościelnicka
990c9b8e11 Add proc_rom pass. 2022-05-13 00:37:14 +02:00
Jannis Harder
fada77b8cf verific: Use new value change logic also for $stable of wide signals. 
I missed this in the previous PR.
 2022-05-11 13:05:27 +02:00
Alastair M. Robinson
83dbea1689 Now calls Tcl_Init after creating the interp, fixes clock format. 2022-05-10 18:48:54 +01:00
github-actions[bot]
c862b1dbfb Bump version 2022-05-10 00:16:26 +00:00
Jannis Harder
587e09d551
Merge pull request #3305 from jix/sva_value_change_logic 
verific: Improve logic generated for SVA value change expressions
 2022-05-09 16:40:34 +02:00
Jannis Harder
5ca2ee0c31
Merge pull request #3297 from jix/sva_nested_clk_else 
verific: Fix conditions of SVAs with explicit clocks within procedures
 2022-05-09 16:07:39 +02:00