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12834 commits 92 branches 52 tags 62 MiB
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104 commits

Author SHA1 Message Date
whitequark 9b39c6f744 cxxrtl: emit debug information for alias wires. 
Alias wires can represent a significant chunk of the design in highly
hierarchical designs; in Minerva SRAM, there are 273 member wires and
527 alias wires. Showing them in every hierarchy level significantly
improves usability.
 2020-06-08 17:09:49 +00:00
whitequark 8262997c4e cxxrtl: fix typo in comment. NFC. 2020-06-08 12:50:35 +00:00
whitequark fb3704c896 cxxrtl: minor debug-related improvements. 2020-06-08 12:50:35 +00:00
whitequark ff5500f11a cxxrtl: rename cxxrtl.cc→cxxrtl_backend.cc. 
To avoid confusion with the C++ source files that are a part of
the simulation itself and not a part of Yosys build.
 2020-06-07 03:48:40 +00:00
Renamed from backends/cxxrtl/cxxrtl.cc (Browse further)