785 commits

Author	SHA1	Message	Date
Eddie Hung	7939727d14	Merge pull request #1660 from YosysHQ/eddie/abc9_unpermute_luts ... Unpermute LUT ordering for ice40/ecp5/xilinx	2020-01-28 11:55:51 -08:00
Eddie Hung	245b8c4ab6	Fix unresolved conflict from #1573	2020-01-28 10:17:47 -08:00
N. Engelhardt	086c133ea5	Merge pull request #1573 from YosysHQ/eddie/xilinx_tristate ... synth_xilinx: error out if tristate without '-iopad'	2020-01-28 17:24:54 +01:00
Eddie Hung	ce6a690d27	xilinx/ice40/ecp5: undo permuting LUT masks in lut_map ... Now done in read_aiger	2020-01-27 13:30:27 -08:00
Eddie Hung	da134701cd	Fix $__ABC9_ASYNC1 to output 1'b1 not 1'b0	2020-01-22 14:22:03 -08:00
Eddie Hung	3d9737c1bd	Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor	2020-01-21 16:27:40 -08:00
Eddie Hung	5c589244df	Deprecate `_CLB_CARRY from +/xilinx/arith_map.v since #1623	2020-01-17 12:02:46 -08:00
Eddie Hung	1e6d56dca1	+/xilinx/arith_map.v fix $lcu rule	2020-01-17 11:28:37 -08:00
Eddie Hung	03ce2c72bb	Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor	2020-01-15 16:42:16 -08:00
Miodrag Milanović	abba1541bc	Merge pull request #1636 from YosysHQ/eddie/fix_synth_xilinx_W ... synth_xilinx: fix default W value for non-xc7	2020-01-15 08:47:16 +01:00
Eddie Hung	d21262ee04	Adding (* techmap_autopurge *) to FD* in abc9_map.v	2020-01-14 12:22:21 -08:00
Eddie Hung	36d1a2c60f	synth_xilinx: fix default W value for non-xc7	2020-01-14 11:34:40 -08:00
Miodrag Milanović	9fbeb57bbd	Merge pull request #1623 from YosysHQ/mmicko/edif_attr ... Export wire properties in EDIF	2020-01-14 19:19:32 +01:00
Eddie Hung	35e49fde4d	Another conflict	2020-01-11 18:57:25 -08:00
Eddie Hung	7d94e18100	synth_xilinx: synth_xilinx.abc9.xc7.W to replace XC7_WIRE_DELAY macro	2020-01-10 15:07:46 -08:00
Miodrag Milanovic	992b507537	Use CARRY4 for abc1 as well, preventing issues with Vivado	2020-01-10 12:34:21 +01:00
Eddie Hung	823a08e0d8	Fix abc9_xc7.box comments	2020-01-07 17:00:38 -08:00
Eddie Hung	5c89dead5f	Merge branch 'master' of github.com:YosysHQ/yosys	2020-01-06 16:51:32 -08:00
Eddie Hung	01866a7909	Fix DSP48E1 sim	2020-01-06 16:45:29 -08:00
Eddie Hung	98ee8c14df	Merge remote-tracking branch 'origin/master' into xaig_dff	2020-01-06 15:02:44 -08:00
Eddie Hung	28bf712372	Wrap arrival functions inside `YOSYS too	2020-01-06 11:55:56 -08:00
Eddie Hung	27c150bfcc	Fix return value of arrival time functions, fix word	2020-01-06 11:39:08 -08:00
Eddie Hung	bac1e65a9c	Fix spacing	2020-01-02 17:21:54 -08:00
Eddie Hung	50b68777d3	Drive $[ABCD] explicitly	2020-01-02 13:28:37 -08:00
Eddie Hung	a051801b72	synth_xilinx -dff to work with abc too	2020-01-02 12:53:26 -08:00
Eddie Hung	3012e9eebc	Merge remote-tracking branch 'origin/master' into eddie/abc9_dsp_refactor	2020-01-02 12:48:07 -08:00
Eddie Hung	b454735bea	Merge remote-tracking branch 'origin/master' into xaig_dff	2020-01-02 12:44:06 -08:00
Eddie Hung	ec1756c094	Update comments	2020-01-02 12:39:52 -08:00
Eddie Hung	8e507bd807	abc9 -keepff -> -dff; refactor dff operations	2020-01-02 12:36:54 -08:00
Eddie Hung	d6242be802	Merge pull request #1601 from YosysHQ/eddie/synth_retime ... "abc -dff" to no longer retime by default	2020-01-02 08:46:24 -08:00
Eddie Hung	d0d3ab8f67	ifndef __ICARUS__ -> ifdef YOSYS	2020-01-01 17:33:47 -08:00
Eddie Hung	3d98a96273	ifdef __ICARUS__ -> ifndef YOSYS	2020-01-01 17:33:10 -08:00
Eddie Hung	db04161eca	Rework abc9's DSP48E1 model	2020-01-01 17:30:26 -08:00
Eddie Hung	0e95756e96	Clamp -46ps for FDPE* too	2020-01-01 08:39:00 -08:00
Eddie Hung	c40b1aae42	Restore abc9 -keepff	2020-01-01 08:34:43 -08:00
Eddie Hung	44d9fb0e7c	Re-arrange FD order	2019-12-31 18:47:38 -08:00
Eddie Hung	35c659be74	Cleanup xilinx boxes	2019-12-31 18:29:44 -08:00
Eddie Hung	6b825c719b	Update abc9_xc7.box comments	2019-12-31 15:25:46 -08:00
Eddie Hung	4cdba00e25	FDCE ports to be alphabetical	2019-12-31 15:24:02 -08:00
Eddie Hung	b4663a987b	Fix attributes on $__ABC9_ASYNC[01] whitebox	2019-12-31 11:14:11 -08:00
Eddie Hung	789211d9b3	Fix incorrect $__ABC9_ASYNC[01] box	2019-12-31 11:13:50 -08:00
Eddie Hung	543bd2de6c	Update timings for Xilinx S7 cells	2019-12-30 14:36:07 -08:00
Eddie Hung	eb4e767053	Do not offset FD* box timings due to -46ps Tsu	2019-12-30 14:35:10 -08:00
Eddie Hung	405e974fe5	Merge remote-tracking branch 'origin/master' into xaig_dff	2019-12-30 14:31:42 -08:00
Eddie Hung	a038294a87	Tidy up abc9_map.v	2019-12-30 14:19:29 -08:00
Eddie Hung	d7ada66497	Add "synth_xilinx -dff" option, cleanup abc9	2019-12-30 14:13:16 -08:00
Eddie Hung	79448f9be0	Update doc that "-retime" calls abc with "-dff -D 1"	2019-12-30 13:28:29 -08:00
Eddie Hung	aa6d06c1b5	Revert "Revert "synth_* with -retime option now calls abc with -D 1 as well"" ... This reverts commit 6008bb7002.	2019-12-30 13:28:29 -08:00
Miodrag Milanovic	8c3de1d4bd	Merge remote-tracking branch 'origin/master' into iopad_default	2019-12-28 16:23:31 +01:00
Marcin Kościelnicki	13a3041030	Merge pull request #1593 from YosysHQ/mwk/dsp48a1-pmgen ... xilinx_dsp: Initial DSP48A/DSP48A1 support.	2019-12-25 16:18:44 +01:00