This website requires JavaScript.
Explore
Help
Register
Sign in
mirrors
/
yosys
Watch
3
Star
0
Fork
You've already forked yosys
0
mirror of
https://github.com/YosysHQ/yosys
synced
2025-07-05 12:25:42 +00:00
Code
Activity
4278
commits
117
branches
55
tags
53
MiB
7850a0c28a
Commit graph
1 commit
Author
SHA1
Message
Date
Clifford Wolf
91dd87e60b
Improved scope resolution of local regs in Verilog+AST frontend
2014-08-05 12:15:53 +02:00