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Code Activity
3766 commits 122 branches 59 tags 72 MiB
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Author SHA1 Message Date
Sergey Kvachonok
963c0d2525 Embed DATDIR make variable value into yosys binary. 
Use it as the last resort in the share/ directory location search.
 2016-03-26 11:16:53 +03:00
Clifford Wolf
a922d705d4 Merge pull request #136 from ravenexp/master 
Minor Makefile adjustments
 2016-03-25 09:16:45 +01:00
Sergey Kvachonok
e14055edf0 Optionally use ${CC} when compiling test utils. 
Default to gcc when not set.
 2016-03-25 10:35:42 +03:00
Sergey Kvachonok
d53a16e43a Allow redefining pkg-config Makefile command. 
Example usage:

$ make CXX=i686-w64-mingw32-g++ PKG_CONFIG=i686-w64-mingw32-pkg-config
 2016-03-25 10:35:42 +03:00
Sergey Kvachonok
972f4a9616 Allow redefining binary and data install locations. 
Add three more Makefile variables in addition to PREFIX:

$ make BINDIR=/.../bin LIBDIR=/.../lib DATDIR=/.../share/yosys

The defaults are:

BINDIR = $(PREFIX)/bin
LIBDIR = $(PREFIX)/lib
DATDIR = $(PREFIX)/share/yosys
 2016-03-25 10:35:42 +03:00
Clifford Wolf
5328a85149 Do not set "nosync" on task outputs, fixes #134 2016-03-24 12:16:47 +01:00
Clifford Wolf
9717495401 Fixed handling of inverters (aka 1-input luts) in nlutmap 2016-03-23 08:56:08 +01:00
Clifford Wolf
b4bf787f10 Added GP_DFFS, GP_DFFR, and GP_DFFSR 2016-03-23 08:46:10 +01:00
Clifford Wolf
456c10f16e Added GP_DFF INIT parameter 2016-03-23 08:12:54 +01:00
Clifford Wolf
4f2ea221dc Added ast.h to exported headers 2016-03-22 14:46:10 +01:00
Clifford Wolf
043fa0fad0 Cleanup abstract modules at end of "hierarchy -top" 2016-03-21 16:37:35 +01:00
Clifford Wolf
2c7e107d7a Support for abstract modules in chparam 2016-03-21 16:37:35 +01:00
Clifford Wolf
4f0d4899ce Added support for $stop system task 2016-03-21 16:19:51 +01:00
Clifford Wolf
ca8f8e30f2 Improvements in synth_greenpak4, added -part option 2016-03-21 09:44:52 +01:00
Clifford Wolf
bb9374b67c Improvements in ABCEXTERNAL handling 2016-03-19 20:02:40 +01:00
Clifford Wolf
b471a32ec3 Merge pull request #130 from ravenexp/master 
Support calling out to an external ABC.
 2016-03-19 19:46:27 +01:00
Sergey Kvachonok
2656b2c55a Support calling out to an external ABC. 
$ make ABCEXTERNAL=my-abc && make ABCEXTERNAL=my-abc install

configures yosys to use an external ABC executable instead of
building and installing the in-tree ABC copy (yosys-abc).
 2016-03-19 18:36:18 +03:00
Clifford Wolf
e5d42ebb4d Added $display %m support, fixed mem leak in $display, fixes #128 2016-03-19 11:51:13 +01:00
Clifford Wolf
ff5c61b120 Added black box modules for all the 7-series design elements (as listed in ug953) 2016-03-19 11:09:10 +01:00
Clifford Wolf
ef4207d5ad Fixed localparam signdness, fixes #127 2016-03-18 12:15:00 +01:00
Clifford Wolf
b6d08f39ba Set "nosync" attribute on internal task/function wires 2016-03-18 10:53:29 +01:00
Clifford Wolf
33c10350b2 Fixed Verilog parser fix and more similar improvements 2016-03-15 12:22:31 +01:00
Andrew Becker
81d4e9e7c1 Use left-recursive rule for cell_port_list in Verilog parser. 2016-03-15 12:03:40 +01:00
Clifford Wolf
2a8d5e64f5 Bugfix in write_verilog for RTLIL processes 2016-03-14 13:03:28 +01:00
Clifford Wolf
dac807fb33 Cleanups and improvements in examples/cmos/ 2016-03-11 11:30:01 +01:00
Clifford Wolf
3265795154 Merge commit 'b34385ec92' 2016-03-11 11:10:44 +01:00
Clifford Wolf
35a6ad4cc1 Fixed typos in verilog_defaults help message 2016-03-10 11:14:51 +01:00
Clifford Wolf
d117893007 Added "write_edif -nogndvcc" 2016-03-08 21:30:45 +01:00
Clifford Wolf
dcd4fb9984 Added examples/cxx-api/evaldemo.cc 2016-03-08 16:54:15 +01:00
Clifford Wolf
e7ed653771 Merge branch 'master' of github.com:cliffordwolf/yosys 2016-03-07 11:17:44 +01:00
Clifford Wolf
c4aaed099f Using "mfs" and "lutpack" in ABC lut mapping 2016-03-07 11:14:11 +01:00
Uros Platise
b34385ec92 Completed ngspice digital example with verilog tb 2016-03-05 08:34:05 +01:00
Clifford Wolf
b0ac32bc03 Added digital (xspice) example code to examples/cmos/ 2016-03-02 12:07:57 +01:00
Clifford Wolf
5547fae4cf Be more conservative with net names in spice output 2016-03-02 12:02:59 +01:00
Clifford Wolf
b36cad75f6 Merge pull request #119 from SebKuzminsky/spelling-fixes 
user-facing spelling fixes
 2016-02-29 10:18:50 +01:00
Sebastian Kuzminsky
7e6426a67d user-facing spelling fixes 
"speciefied" -> "specified"
"unkown" -> "unknown"
 2016-02-28 15:14:01 -07:00
Clifford Wolf
c89f61c730 We are now in 0.6+ development 2016-02-26 17:24:31 +01:00
Clifford Wolf
5869d26da0 Yosys 0.6 2016-02-26 16:55:21 +01:00
Clifford Wolf
22c549ab37 Fixed BLIF parser for empty port assignments 2016-02-24 09:16:43 +01:00
Clifford Wolf
45af4a4acf Use easyer-to-read unoptimized ceil_log2() 
see here for details on the optimized version:
http://svn.clifford.at/handicraft/2016/esbmc/ceilog2.c
 2016-02-15 23:06:18 +01:00
Clifford Wolf
7a9257e7b5 Updated ABC to ae7d65e71adc 2016-02-15 15:30:46 +01:00
Clifford Wolf
85fe6d176f Updated command reference in manual 2016-02-14 11:02:11 +01:00
Clifford Wolf
0761ad6e18 Changelog for upcoming 0.6 release 2016-02-14 10:50:19 +01:00
Clifford Wolf
0c4b311242 Fixed more visual studio warnings 2016-02-14 09:35:25 +01:00
Clifford Wolf
bcc873b805 Fixed some visual studio warnings 2016-02-13 17:31:24 +01:00
Clifford Wolf
6f1d694171 Merge branch 'master' of github.com:cliffordwolf/yosys 2016-02-13 17:01:29 +01:00
Clifford Wolf
0d7fd2585e Added "int ceil_log2(int)" function 2016-02-13 16:52:16 +01:00
Clifford Wolf
0373bd98bb Fixed MXE ABC build 2016-02-13 15:43:23 +01:00
Clifford Wolf
a75f94ec4a Run dffsr2dff in synth_xilinx 2016-02-13 08:20:19 +01:00
Clifford Wolf
7bd329afa0 Support for more Verific primitives (patch I got per email) 2016-02-13 08:19:30 +01:00