628 commits

Author	SHA1	Message	Date
Clifford Wolf	0b72f0acb1	Basic $macc extract in alumacc	2014-09-14 10:45:28 +02:00
Clifford Wolf	ff157fb74f	alumacc skeleton	2014-09-14 10:02:00 +02:00
Clifford Wolf	d46bac3305	Added "$fa" cell type	2014-09-08 12:15:39 +02:00
Clifford Wolf	1a88e47396	Trim msb/lsb zero bits from full adder in maccmap	2014-09-08 11:21:58 +02:00
Clifford Wolf	c50b841b29	Added 'techmap_maccmap' techmap attribute	2014-09-07 18:23:37 +02:00
Clifford Wolf	015dcdc84c	Added "maccmap" command	2014-09-07 18:23:04 +02:00
Clifford Wolf	8927aa6148	Removed $bu0 cell type	2014-09-04 02:07:52 +02:00
Clifford Wolf	826fdb34d8	Added "techmap -autoproc"	2014-09-01 15:36:29 +02:00
Clifford Wolf	d148b0af0d	Fixed inserting of Q-inverters in dfflibmap	2014-08-27 19:44:12 +02:00
Clifford Wolf	c642dd0b3e	Only call proc_share_dirname() in techmap when necessary	2014-08-23 15:32:00 +02:00
Clifford Wolf	19cff41eb4	Changed frontend-api from FILE to std::istream	2014-08-23 15:03:55 +02:00
Clifford Wolf	5dce303a2a	Changed backend-api from FILE to std::ostream	2014-08-23 13:54:21 +02:00
Clifford Wolf	410d043dd8	Renamed toposort.h to utils.h	2014-08-17 00:55:35 +02:00
Clifford Wolf	674f421b47	Bugfix in iopadmap	2014-08-15 14:29:42 +02:00
Clifford Wolf	f092b50148	Renamed $_INV_ cell type to $_NOT_	2014-08-15 14:11:40 +02:00
Clifford Wolf	ca87116449	More idstring sort_by_* helpers and fixed tpl ordering in techmap	2014-08-15 02:40:46 +02:00
Clifford Wolf	d320e75087	document "techmap -map %<design-name>"	2014-08-15 02:01:30 +02:00
Clifford Wolf	1bf7a18fec	Added module->ports	2014-08-14 16:22:52 +02:00
Clifford Wolf	014a41fcf3	Implemented recursive techmap	2014-08-03 12:40:43 +02:00
Clifford Wolf	08ec33a5e5	Implemented simplemap support for "techmap -extern"	2014-08-02 21:55:13 +02:00
Clifford Wolf	b6acbc82e6	Bugfix in "techmap -extern"	2014-08-02 20:54:30 +02:00
Clifford Wolf	04727c7e0f	No implicit conversion from IdString to anything else	2014-08-02 18:58:40 +02:00
Clifford Wolf	768eb846c4	More bugfixes related to new RTLIL::IdString	2014-08-02 18:14:21 +02:00
Clifford Wolf	b9bd22b8c8	More cleanups related to RTLIL::IdString usage	2014-08-02 13:19:57 +02:00
Clifford Wolf	bd74ed7da4	Replaced sha1 implementation	2014-08-01 19:01:10 +02:00
Clifford Wolf	cdae8abe16	Renamed port access function on RTLIL::Cell, added param access functions	2014-07-31 16:38:54 +02:00
Clifford Wolf	e6d33513a5	Added module->design and cell->module, wire->module pointers	2014-07-31 14:11:39 +02:00
Clifford Wolf	1cb25c05b3	Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace	2014-07-31 13:19:47 +02:00
Clifford Wolf	1202f7aa4b	Renamed "stdcells.v" to "techmap.v"	2014-07-31 02:32:00 +02:00
Clifford Wolf	6ca0c569d9	Added "techmap -assert"	2014-07-31 02:21:41 +02:00
Clifford Wolf	2541489105	Added techmap CONSTMAP feature	2014-07-30 22:04:30 +02:00
Clifford Wolf	03c96f9ce7	Added "techmap -map %{design-name}"	2014-07-29 16:35:13 +02:00
Clifford Wolf	7bd2d1064f	Using log_assert() instead of assert()	2014-07-28 11:27:48 +02:00
Clifford Wolf	8b0f50792c	Added techmap -extern	2014-07-27 21:31:18 +02:00
Clifford Wolf	5da343b7de	Added topological sorting to techmap	2014-07-27 16:43:39 +02:00
Clifford Wolf	49f72421d5	Using new obj iterator API in a few places	2014-07-27 11:32:42 +02:00
Clifford Wolf	10e5791c5e	Refactoring: Renamed RTLIL::Design::modules to modules_	2014-07-27 11:18:30 +02:00
Clifford Wolf	4c4b602156	Refactoring: Renamed RTLIL::Module::cells to cells_	2014-07-27 01:51:45 +02:00
Clifford Wolf	f9946232ad	Refactoring: Renamed RTLIL::Module::wires to wires_	2014-07-27 01:49:51 +02:00
Clifford Wolf	d68c993ed2	Changed more code to the new RTLIL::Wire constructors	2014-07-26 21:30:38 +02:00
Clifford Wolf	3f4e3ca8ad	More RTLIL::Cell API usage cleanups	2014-07-26 16:14:02 +02:00
Clifford Wolf	f8fdc47d33	Manual fixes for new cell connections API	2014-07-26 15:58:23 +02:00
Clifford Wolf	b7dda72302	Changed users of cell->connections_ to the new API (sed command) ... git grep -l 'connections_' | xargs sed -i -r -e ' s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g; s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g; s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g; s/(->|\.)connections_.push_back/\1connect/g; s/(->|\.)connections_/\1connections()/g;'	2014-07-26 15:58:23 +02:00
Clifford Wolf	cc4f10883b	Renamed RTLIL::{Module,Cell}::connections to connections_	2014-07-26 11:58:03 +02:00
Clifford Wolf	4755e14e7b	Added copy-constructor-like module->addCell(name, other) method	2014-07-26 00:38:44 +02:00
Clifford Wolf	2bec47a404	Use only module->addCell() and module->remove() to create and delete cells	2014-07-25 17:56:19 +02:00
Clifford Wolf	45b4154b37	Added "make SMALL=1"	2014-07-24 19:03:57 +02:00
Clifford Wolf	b17d6531c8	Added "make PRETTY=1"	2014-07-24 17:15:01 +02:00
Clifford Wolf	a62c21c9c6	Removed RTLIL::SigSpec::expand() method	2014-07-23 19:34:51 +02:00
Clifford Wolf	4e802eb7f6	Fixed all users of SigSpec::chunks_rw() and removed it	2014-07-23 15:36:09 +02:00