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									 Clifford Wolf | 0bc95f1e04 | Added "yosys -D" feature | 2016-04-21 23:28:37 +02:00 |  | 
				
					
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									 Clifford Wolf | eaac5bfbc7 | Improved formatting of "sat" output tables | 2016-04-05 08:26:10 +02:00 |  | 
				
					
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									 Clifford Wolf | 1d0f0d668a | Renamed opt_const to opt_expr | 2016-03-31 08:46:56 +02:00 |  | 
				
					
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									 Clifford Wolf | 207736b4ee | Import more std:: stuff into Yosys namespace | 2015-10-25 19:30:49 +01:00 |  | 
				
					
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									 Clifford Wolf | 7f110e7018 | renamed SigSpec::to_single_sigbit() to SigSpec::as_bit(), added is_bit() | 2015-10-24 22:56:40 +02:00 |  | 
				
					
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									 Clifford Wolf | f40d1b78b6 | Added sat -show-regs, -show-public, -show-all | 2015-08-18 17:14:30 +02:00 |  | 
				
					
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									 Clifford Wolf | 0350074819 | Re-created command-reference-manual.tex, copied some doc fixes to online help | 2015-08-14 11:27:19 +02:00 |  | 
				
					
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									 Clifford Wolf | 84bf862f7c | Spell check (by Larry Doolittle) | 2015-08-14 10:56:05 +02:00 |  | 
				
					
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									 Clifford Wolf | badc5f7eb9 | Added "miter -assert" | 2015-07-25 12:09:57 +02:00 |  | 
				
					
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									 Clifford Wolf | 6c84341f22 | Fixed trailing whitespaces | 2015-07-02 11:14:30 +02:00 |  | 
				
					
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									 Clifford Wolf | ee9188a5b4 | Added logic-loop error handling to freduce | 2015-06-30 17:11:46 +02:00 |  | 
				
					
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									 Clifford Wolf | faa95dd845 | don't consider blackbox modules in "sat" command | 2015-04-18 09:29:03 +02:00 |  | 
				
					
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									 Clifford Wolf | 1f1deda888 | Added non-std verilog assume() statement | 2015-02-26 18:47:39 +01:00 |  | 
				
					
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									 Clifford Wolf | 39d25b212c | Fixed "sat -initsteps" off-by-one bug | 2015-02-22 12:42:05 +01:00 |  | 
				
					
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									 Clifford Wolf | fae0e75ace | Added "sat -stepsize" and "sat -tempinduct-step" | 2015-02-21 22:52:49 +01:00 |  | 
				
					
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									 Clifford Wolf | b19c926af8 | sat docu change | 2015-02-21 22:03:54 +01:00 |  | 
				
					
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									 Clifford Wolf | 9237fb924e | When "sat -tempinduct-baseonly -maxsteps N" reaches maxsteps it is a good thing. | 2015-02-21 20:05:16 +01:00 |  | 
				
					
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									 Clifford Wolf | 1688b9b464 | Added "sat -tempinduct-baseonly -tempinduct-inductonly" | 2015-02-21 17:53:22 +01:00 |  | 
				
					
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									 Clifford Wolf | dcbd00c101 | Fixed basecase init for "sat -tempinduct" | 2015-02-21 17:43:49 +01:00 |  | 
				
					
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									 Clifford Wolf | 4e6ca7760f | Replaced ezDefaultSAT with ezSatPtr | 2015-02-21 12:15:41 +01:00 |  | 
				
					
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									 Clifford Wolf | 08c0fe164f | format fixes in "sat -dump_json" | 2015-02-19 13:19:04 +01:00 |  | 
				
					
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									 Clifford Wolf | 1ecee6c49c | Added "sat -dump_json" (WaveJSON format) | 2015-02-19 10:53:40 +01:00 |  | 
				
					
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									 Clifford Wolf | 9ebf803cbe | Improved an error message | 2015-01-28 00:46:00 +01:00 |  | 
				
					
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									 Clifford Wolf | 23e54bda81 | Added "sat -show-ports" | 2015-01-27 23:04:28 +00:00 |  | 
				
					
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									 Clifford Wolf | 0a225f8b27 | Moved equiv stuff to passes/equiv/ | 2015-01-22 12:03:15 +01:00 |  | 
				
					
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									 Clifford Wolf | abf8398216 | Progress in equiv_simple | 2015-01-21 23:59:58 +00:00 |  | 
				
					
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									 Clifford Wolf | 5febbe3620 | Added equiv_simple | 2015-01-19 15:08:44 +01:00 |  | 
				
					
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									 Clifford Wolf | 615c2e136e | Added equiv_status | 2015-01-19 14:20:04 +01:00 |  | 
				
					
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									 Clifford Wolf | 76c5d863c5 | Added equiv_make command | 2015-01-19 13:59:08 +01:00 |  | 
				
					
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									 Clifford Wolf | edb3c9d0c4 | Renamed extend() to extend_xx(), changed most users to extend_u0() | 2014-12-24 09:51:17 +01:00 |  | 
				
					
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									 Clifford Wolf | fe829bdbdc | Added log_warning() API | 2014-11-09 10:44:23 +01:00 |  | 
				
					
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									 Clifford Wolf | 7cb0d3aa1a | Renamed TRUE/FALSE to CONST_TRUE/CONST_FALSE because of name collision on Win32 | 2014-10-10 17:07:24 +02:00 |  | 
				
					
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									 Clifford Wolf | 4569a747f8 | Renamed SIZE() to GetSize() because of name collision on Win32 | 2014-10-10 17:07:24 +02:00 |  | 
				
					
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									 Clifford Wolf | f9a307a50b | namespace Yosys | 2014-09-27 16:17:53 +02:00 |  | 
				
					
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									 Ruben Undheim | 79cbf9067c | Corrected spelling mistakes found by lintian | 2014-09-06 08:47:06 +02:00 |  | 
				
					
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									 Clifford Wolf | 27a1bfbec6 | Fixes in old SAT example.ys | 2014-09-01 11:45:47 +02:00 |  | 
				
					
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									 Clifford Wolf | d5148f2e01 | Moved "share" and "wreduce" to passes/opt/ | 2014-09-01 11:45:26 +02:00 |  | 
				
					
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									 Clifford Wolf | 9c5a63c52c | azonenberg: Make dump_vcd save model when temporal induction fails due to step limit | 2014-08-24 13:27:40 +02:00 |  | 
				
					
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									 Clifford Wolf | f092b50148 | Renamed $_INV_ cell type to $_NOT_ | 2014-08-15 14:11:40 +02:00 |  | 
				
					
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									 Clifford Wolf | 9d4362990f | Fixed "share" for complex scenarios with never-active cells | 2014-08-09 17:07:20 +02:00 |  | 
				
					
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									 Clifford Wolf | b9811d5aff | Do not share any $reduce_* cells (its complicated and not worth it anyways) | 2014-08-09 15:40:25 +02:00 |  | 
				
					
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									 Clifford Wolf | cb6ca08a53 | Fixed sharing of reduce operator | 2014-08-08 14:24:09 +02:00 |  | 
				
					
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									 Clifford Wolf | 622ebab671 | Added "sat -prove-skip" | 2014-08-08 13:11:54 +02:00 |  | 
				
					
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									 Clifford Wolf | c55eb8f8a6 | Use "-keepdc" in "miter -equiv -flatten" | 2014-08-07 16:42:35 +02:00 |  | 
				
					
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									 Clifford Wolf | c7f99be3be | Fixed "share" for memory read ports | 2014-08-03 20:22:33 +02:00 |  | 
				
					
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									 Clifford Wolf | 8e7361f128 | Removed at() method from RTLIL::IdString | 2014-08-02 19:08:02 +02:00 |  | 
				
					
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									 Clifford Wolf | 768eb846c4 | More bugfixes related to new RTLIL::IdString | 2014-08-02 18:14:21 +02:00 |  | 
				
					
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									 Clifford Wolf | b9bd22b8c8 | More cleanups related to RTLIL::IdString usage | 2014-08-02 13:19:57 +02:00 |  | 
				
					
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									 Clifford Wolf | 32a1cc3efd | Renamed modwalker.h to modtools.h | 2014-07-31 23:30:18 +02:00 |  | 
				
					
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									 Clifford Wolf | cdae8abe16 | Renamed port access function on RTLIL::Cell, added param access functions | 2014-07-31 16:38:54 +02:00 |  |