mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-28 19:35:53 +00:00
Code Activity
4473 commits 102 branches 53 tags 48 MiB
Commit graph

4473 commits

This branch
This branch
All branches
Author SHA1 Message Date
Clifford Wolf
6e00c217ae After release is before release 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-10-16 16:44:58 +02:00
Clifford Wolf
4d4665b23a Merge branch 'yosys-0.8-rc' 2018-10-16 16:40:10 +02:00
Clifford Wolf
5706e90802 Yosys 0.8 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-10-16 16:22:16 +02:00
argama
097da32e1a ignore protect endprotect 2018-10-16 21:33:37 +08:00
Clifford Wolf
500726781b Update command reference manual 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-10-16 15:28:37 +02:00
David Shah
df4bfa0ad6 ecp5: Disable LSR inversion 
Signed-off-by: David Shah <dave@ds0.me>
 2018-10-16 12:48:39 +01:00
Aman Goel
749b3ed62a Minor update 2018-10-15 13:54:12 -04:00
Ruben Undheim
736105b046 Handle FIXME for modport members without type directly in front 2018-10-13 20:50:33 +02:00
Ruben Undheim
c50afc4246 Documentation improvements etc. 
- Mention new feature in the SystemVerilog section in the README file
- Commented changes much better
- Rename a few signals to make it clearer
- Prevent warning for unused signals in an easier way
- Add myself as copyright holder to 2 files
- Fix one potential memory leak (delete 'wire' if not in modport)
 2018-10-13 20:34:44 +02:00
argama
455638e00d detect ff/latch before processing other nodes 2018-10-14 01:42:48 +08:00
tklam
f4343b3dc7 stop check_signal_in_fanout from traversing FFs 2018-10-13 23:24:24 +08:00
tklam
302edf0429 stop check_signal_in_fanout from traversing FFs 2018-10-13 23:11:19 +08:00
tklam
3c5406c31b Merge branch 'master' of https://github.com/YosysHQ/yosys 2018-10-13 22:52:31 +08:00
Ruben Undheim
a36d1701dd Fix build error with clang 2018-10-12 22:14:49 +02:00
Ruben Undheim
458a94059e Support for 'modports' for System Verilog interfaces 2018-10-12 21:11:48 +02:00
Ruben Undheim
75009ada3c Synthesis support for SystemVerilog interfaces 
This time doing the changes mostly in AST before RTLIL generation
 2018-10-12 21:11:36 +02:00
David Shah
812538a036 BRAM improvements 
Signed-off-by: David Shah <dave@ds0.me>
 2018-10-12 14:22:21 +01:00
David Shah
bdfead8c64 ecp5: Adding BRAM maps for all size options 
Signed-off-by: David Shah <dave@ds0.me>
 2018-10-10 17:18:17 +01:00
David Shah
983fb7ff88 ecp5: First BRAM type maps successfully 
Signed-off-by: David Shah <dave@ds0.me>
 2018-10-10 16:35:19 +01:00
David Shah
2ef1af8b58 ecp5: Script for BRAM IO connections 
Signed-off-by: David Shah <dave@ds0.me>
 2018-10-10 16:11:00 +01:00
David Shah
346cbbdbdc ecp5: Adding BRAM initialisation and config 
Signed-off-by: David Shah <dave@ds0.me>
 2018-10-09 14:19:04 +01:00
Tim 'mithro' Ansell
b111ea1228 xilinx: Still map LUT7/LUT8 to Xilinx specific primitives. 
Then if targeting vpr map all the Xilinx specific LUTs back into generic
Yosys LUTs.
 2018-10-08 16:52:12 -07:00
Clifford Wolf
3bb9288d65 Improve Verific importer blackbox handling 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-10-08 11:38:10 -07:00
Clifford Wolf
8e13f2913d Add "write_edif -attrprop" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-10-08 11:38:10 -07:00
Clifford Wolf
05e1c39064 Fix compiler warning in verific.cc 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-10-08 11:38:10 -07:00
Tim Ansell
3661c27acd Fix misspelling in issue_template.md 
It's been bugging me :-P
 2018-10-08 11:38:10 -07:00
Adrian Wheeldon
81d77c4911 Fix IdString M in setup_stdcells() 2018-10-08 11:38:10 -07:00
Clifford Wolf
ea82191c57 Add inout ports to cells_xtra.v 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-10-08 11:38:10 -07:00
Tim Ansell
cd261795ba xilinx: Adding missing inout IO port to IOBUF 2018-10-08 11:38:10 -07:00
Tom Verbeure
b8950bd603 Fix for issue 594. 2018-10-08 11:38:10 -07:00
Dan Gisselquist
d3be61b9dc Add read_verilog $changed support 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-10-08 11:38:10 -07:00
David Shah
ae8637cd63 ecp5: Don't map ROMs to DRAM 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-10-08 11:38:10 -07:00
Clifford Wolf
7d88d851d8 Fix handling of $past 2nd argument in read_verilog 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-10-08 11:38:10 -07:00
Clifford Wolf
b3de38d357 Update to v2 YosysVS template 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-10-08 11:38:10 -07:00
Clifford Wolf
89ef6600bc Add "read_verilog -noassert -noassume -assert-assumes" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-10-08 11:38:10 -07:00
Clifford Wolf
e8431d1508 Added support for ommited "parameter" in Verilog-2001 style parameter decl in SV mode 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-10-08 11:38:10 -07:00
Clifford Wolf
a9085ff4af Update CHANGELOG 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-10-08 11:38:10 -07:00
Miodrag Milanovic
6cf9fca93b added prefix to FDirection constants, fixing windows build 2018-10-08 11:38:10 -07:00
Clifford Wolf
f73e7116f9 Update CHANGLELOG 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-10-08 11:38:10 -07:00
Clifford Wolf
8340d44986 Update Changelog 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-10-08 11:38:10 -07:00
Miodrag Milanovic
24951ddc77 Fix Cygwin build and document needed packages 2018-10-08 11:38:10 -07:00
acw1251
33ac82a5fe Fixed typo in "verilog_write" help message 2018-10-08 11:38:10 -07:00
Clifford Wolf
9850de405a Improve Verific importer blackbox handling 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-10-07 19:48:55 +02:00
David Shah
31e22c8b96 ecp5: Add blackbox for DP16KD 
Signed-off-by: David Shah <dave@ds0.me>
 2018-10-05 11:35:59 +01:00
Clifford Wolf
ed1f0b2577
Merge pull request #651 from ARandomOWL/stdcells_fix 
Fix IdString M in setup_stdcells()
 2018-10-05 09:59:57 +02:00
Clifford Wolf
115ca57647 Add "write_edif -attrprop" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-10-05 09:41:30 +02:00
Clifford Wolf
257a846113
Merge pull request #654 from mithro/patch-1 
Fix misspelling in issue_template.md
 2018-10-05 09:29:26 +02:00
Clifford Wolf
4b0448fc2c Fix compiler warning in verific.cc 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-10-05 09:26:10 +02:00
Tim Ansell
63d53006cb
Fix misspelling in issue_template.md 
It's been bugging me :-P
 2018-10-04 17:15:30 -07:00
Adrian Wheeldon
1355492c89 Fix IdString M in setup_stdcells() 2018-10-04 15:36:26 +01:00