9 commits

Author	SHA1	Message	Date
Clifford Wolf	6c84341f22	Fixed trailing whitespaces	2015-07-02 11:14:30 +02:00
Clifford Wolf	aa0ab975b9	Removed "techmap -share_map" (use "-map +/filename" instead)	2015-04-08 12:13:53 +02:00
Ahmed Irfan	d3c67ad9b6	Merge branch 'master' of https://github.com/cliffordwolf/yosys into btor ... added case for memwr cell that is used in muxes (same cell is used more than one time) corrected bug for xnor and logic_not added pmux cell translation Conflicts: backends/btor/btor.cc	2014-09-22 11:35:04 +02:00
Ahmed Irfan	ac896c63e2	modified btor synthesis script for correct use of splice command.	2014-02-12 13:38:28 +01:00
Ahmed Irfan	45e468114a	disabling splice command in the script	2014-02-11 15:43:03 +01:00
Ahmed Irfan	e8f6b8f201	added concat and slice cell translation	2014-02-11 13:06:01 +01:00
Clifford Wolf	a6750b3753	Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)	2014-02-03 13:01:45 +01:00
Clifford Wolf	210dda286f	Use techmap -share_map in btor scripts	2014-01-24 15:52:16 +01:00
Clifford Wolf	6804edd5d4	Moved btor scripts to backends/btor/	2014-01-24 15:48:07 +01:00

Renamed from verilog2btor.sh (Browse further)