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									 Clifford Wolf | d1e38693d5 | More Xilinx bram cleanups | 2015-01-07 01:59:36 +01:00 |  | 
				
					
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									 Clifford Wolf | 584c5f3937 | Cleanups in xilinx bram descriptions | 2015-01-07 01:28:18 +01:00 |  | 
				
					
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									 Clifford Wolf | 08c13f635c | Xilinx RAMB36/RAMB18 memory_bram support complete | 2015-01-06 23:54:33 +01:00 |  | 
				
					
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									 Clifford Wolf | ec2eef89fa | Towards Xilinx bram support | 2015-01-06 23:21:52 +01:00 |  | 
				
					
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									 Clifford Wolf | 7cc5192125 | small fix in xilinx/brams.v | 2015-01-06 17:21:18 +01:00 |  | 
				
					
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									 Clifford Wolf | 9474928672 | Towards Xilinx bram support | 2015-01-06 15:26:33 +01:00 |  | 
				
					
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									 Clifford Wolf | 4a0b3a5423 | Various small improvements to synth_xilinx | 2015-01-06 14:37:50 +01:00 |  | 
				
					
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									 Clifford Wolf | 081e1a49f8 | Towards Xilinx bram support | 2015-01-06 14:26:51 +01:00 |  | 
				
					
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									 Clifford Wolf | 9c7f47bbd5 | Towards Xilinx bram support | 2015-01-06 13:33:51 +01:00 |  | 
				
					
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									 Clifford Wolf | 9ea2511fe8 | Towards Xilinx bram support | 2015-01-05 13:59:04 +01:00 |  | 
				
					
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									 Clifford Wolf | 8898897f7b | Towards Xilinx bram support | 2015-01-04 14:23:30 +01:00 |  | 
				
					
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									 Clifford Wolf | 327a5d42b6 | Progress in memory_bram | 2014-12-31 22:50:08 +01:00 |  | 
				
					
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									 Clifford Wolf | 94e6b70736 | Added memory_bram (not functional yet) | 2014-12-31 16:53:53 +01:00 |  | 
				
					
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									 Clifford Wolf | f9a307a50b | namespace Yosys | 2014-09-27 16:17:53 +02:00 |  | 
				
					
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									 Clifford Wolf | b64b38eea2 | Renamed $lut ports to follow A-Y naming scheme | 2014-08-15 14:18:40 +02:00 |  | 
				
					
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									 Clifford Wolf | b17d6531c8 | Added "make PRETTY=1" | 2014-07-24 17:15:01 +02:00 |  | 
				
					
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									 Clifford Wolf | 20175afd29 | Added "techmap -share_map" option | 2013-11-24 19:50:25 +01:00 |  | 
				
					
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									 Clifford Wolf | ae798d3fd5 | Fixed xilinx/example_sim_counter test bench | 2013-11-24 17:55:46 +01:00 |  | 
				
					
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									 Clifford Wolf | 532091afcb | Added more generic _TECHMAP_ wire mechanism to techmap pass | 2013-11-23 15:58:06 +01:00 |  | 
				
					
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									 James Walmsley | 40b3551b45 | [EXAMPLES] Ported the mojo counter example to Zynq ZED board. Will be adding a tutorial on this to verilog.james.walms.co.uk in a few days. | 2013-10-27 21:48:39 +01:00 |  | 
				
					
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									 Clifford Wolf | 88cd2eadf5 | Cleanups in xilinx examples | 2013-10-27 09:58:53 +01:00 |  | 
				
					
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									 Clifford Wolf | 4a3669d871 | Added synth_xilinx command | 2013-10-27 09:51:06 +01:00 |  | 
				
					
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									 Clifford Wolf | 90b016716b | Moved simple xilinx counter sim example to subdir | 2013-10-27 09:30:17 +01:00 |  | 
				
					
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									 Clifford Wolf | 02f321b6fc | Xilinx mojo_counter example is now working | 2013-10-27 08:21:56 +01:00 |  | 
				
					
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									 Clifford Wolf | d635f8adaa | Renamed techlibs/xilinx7 to techlibs/xilinx | 2013-10-26 22:29:40 +02:00 |  |