mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-01-21 09:34:44 +00:00
Code Activity
4433 commits 122 branches 63 tags 51 MiB
Commit graph

4 commits

Author SHA1 Message Date
Clifford Wolf
979de95cf6
Merge pull request #750 from Icenowy/anlogic-ff-init 
Initialization of Anlogic DFFs
 2019-01-02 15:52:22 +01:00
Icenowy Zheng
1b36944299 anlogic: add latch cells 
Add latch cells to Anlogic cells replacement library by copying other
FPGAs' latch code to it.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
 2018-12-25 22:47:46 +08:00
Icenowy Zheng
4bf8ac728c anlogic: set the init value of DFFs 
As dffinit has already supported for different initialization strings
for DFFs and check for re-initialization, initialization of Anlogic
DFFs are now ready to go.

Support for set the init values of Anlogic DFFs.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
 2018-12-18 23:16:37 +08:00
Miodrag Milanovic
83bce9f59c Initial support for Anlogic FPGA 2018-12-01 18:28:54 +01:00