3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-27 19:05:52 +00:00
Commit graph

309 commits

Author SHA1 Message Date
Eddie Hung
f433a52374 Add FIXME about need for -mux4 2019-06-21 11:15:23 -07:00
Eddie Hung
dd22edcd28 Expand synth -coarse without wreduce, move muxcover 2019-06-21 11:12:32 -07:00
Eddie Hung
f11c9a419b Call opt_expr -mux_undef to get rid of 1'bx in muxes prior to abc 2019-06-20 17:38:16 -07:00
Eddie Hung
d1dadfcec8 Call opt_expr -mux_undef to get rid of 1'bx in muxes prior to abc 2019-06-20 16:45:09 -07:00
Eddie Hung
5ce672d1c5 Merge remote-tracking branch 'origin/xaig' into xaig_dff 2019-06-17 12:14:55 -07:00
Eddie Hung
c15ee827f4 Try -W 300 2019-06-17 10:29:06 -07:00
Eddie Hung
1ec450d6bf Try -W 300 2019-06-16 12:08:03 -07:00
Eddie Hung
a76c8a7ffd Fix initialisation of flops 2019-06-15 09:46:35 -07:00
Eddie Hung
ac18a76beb Map to $_FF_ instead of $_DFF_P_ to prevent recursion issues 2019-06-15 09:34:48 -07:00
Eddie Hung
295bb23ae0 Wrap FDRE with $__ABC_FDRE containing comb 2019-06-15 09:08:56 -07:00
Eddie Hung
b63b2a0bd4 Revert "Remove wide mux inference"
This reverts commit 738fdfe8f5.
2019-06-14 12:50:24 -07:00
Eddie Hung
2e34859a6b Add XC7_WIRE_DELAY macro to synth_xilinx.cc 2019-06-14 11:38:22 -07:00
Eddie Hung
d47ff7ba87 Rename +/xilinx/abc.{box,lut} -> abc_xc7.{box,lut} 2019-06-14 10:51:11 -07:00
Eddie Hung
627a62a797 Make doc consistent 2019-06-14 10:32:46 -07:00
Eddie Hung
c7f5091c2f Reduce diff with master 2019-06-12 09:34:41 -07:00
Eddie Hung
99267f660f Fix spacing 2019-06-12 09:21:52 -07:00
Eddie Hung
738fdfe8f5 Remove wide mux inference 2019-06-12 09:20:46 -07:00
Eddie Hung
f7a9769c14 Merge remote-tracking branch 'origin/master' into xaig 2019-06-12 08:50:39 -07:00
Eddie Hung
02973474df Remove extra newline 2019-06-03 20:04:47 -07:00
Eddie Hung
0ad50332d9 Execute techmap and arith_map simultaneously 2019-06-03 19:36:09 -07:00
Clifford Wolf
04ef222cfb Add "stat -tech xilinx"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-11 09:24:52 +02:00
Clifford Wolf
09467bb9a3 Add "synth_xilinx -arch"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-07 15:04:36 +02:00
Eddie Hung
d394b9301b Back to passing all xc7srl tests! 2019-05-01 18:23:21 -07:00
Eddie Hung
31ff0d8ef5 Merge remote-tracking branch 'origin/master' into eddie/synth_xilinx_fine 2019-05-01 18:09:38 -07:00
Marcin Kościelnicki
98e5a625c4 synth_xilinx: Add -nocarry and -nomux options. 2019-04-30 12:54:21 +02:00
Eddie Hung
e97178a888 WIP 2019-04-28 12:51:00 -07:00
Eddie Hung
d855683917 Revert synth_xilinx 'fine' label more to how it used to be... 2019-04-26 16:53:16 -07:00
Eddie Hung
ea0e0722bb Where did this check come from!?! 2019-04-26 15:35:34 -07:00
Eddie Hung
727eec04c5 Refactor synth_xilinx to auto-generate doc 2019-04-26 14:32:18 -07:00
Eddie Hung
0bd2bfa737 Merge remote-tracking branch 'origin/master' into xaig 2019-04-22 18:15:28 -07:00
Eddie Hung
ec88129a5c Update help message 2019-04-22 11:38:23 -07:00
Eddie Hung
4883391b63 Merge remote-tracking branch 'origin/master' into xaig 2019-04-22 11:19:52 -07:00
Eddie Hung
0e76718720 Move 'shregmap -tech xilinx' into map_cells 2019-04-22 10:45:39 -07:00
Eddie Hung
e300b1922c Merge remote-tracking branch 'origin/master' into xc7srl 2019-04-22 10:36:27 -07:00
Clifford Wolf
cf1ba46fa0 Re-added clean after techmap in synth_xilinx
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-22 09:03:11 +02:00
Eddie Hung
d342b5b135 Tidy up, fix for -nosrl 2019-04-21 15:33:03 -07:00
Eddie Hung
726e2da8f2 Merge branch 'map_cells_before_map_luts' into xc7srl 2019-04-21 14:28:55 -07:00
Eddie Hung
a3371e118b Merge branch 'master' into map_cells_before_map_luts 2019-04-21 14:24:50 -07:00
Eddie Hung
ae95aba60a Add comments 2019-04-21 14:16:59 -07:00
Eddie Hung
d99422411f Use new pmux2shiftx from #944, remove my old attempt 2019-04-21 14:16:34 -07:00
Eddie Hung
caec7f9d2c Merge remote-tracking branch 'origin/master' into xaig 2019-04-20 12:23:49 -07:00
Eddie Hung
6008bb7002 Revert "synth_* with -retime option now calls abc with -D 1 as well"
This reverts commit 9a6da9a79a.
2019-04-18 07:59:16 -07:00
Eddie Hung
04e466d5e4 Add support for synth_xilinx -abc9 and ignore abc9 -dress opt 2019-04-12 12:28:37 -07:00
Eddie Hung
9a6da9a79a synth_* with -retime option now calls abc with -D 1 as well 2019-04-10 08:32:53 -07:00
Eddie Hung
1d526b7f06 Call shregmap twice -- once for variable, another for fixed 2019-04-05 17:35:49 -07:00
Eddie Hung
a5f33b5409 Move dffinit til after abc 2019-04-05 16:20:43 -07:00
Eddie Hung
0364a5d811 Merge branch 'eddie/fix_retime' into xc7srl 2019-04-05 15:46:18 -07:00
Eddie Hung
9758701574 Move techamp t:$_DFF_?N? to before abc call 2019-04-05 15:39:05 -07:00
Eddie Hung
8b6085254a Resolve @daveshah1 comment, update synth_xilinx help 2019-04-05 15:15:13 -07:00
Eddie Hung
ff0912c75e synth_xilinx to techmap FFs after abc call, otherwise -retime fails 2019-04-05 14:43:06 -07:00