Eddie Hung
b7afafde22
Consistency
2019-12-27 14:52:26 -08:00
Eddie Hung
5017be6445
Cope with abc9_arrival as string
2019-12-27 14:49:09 -08:00
Eddie Hung
4eaa45091c
Update some abc9_arrival times, add abc9_required times
2019-12-27 14:47:50 -08:00
Eddie Hung
49881b4468
write_xaiger: fix arrival times for non boxes
2019-12-27 11:30:18 -08:00
Miodrag Milanovic
3e14ff1667
fixed invalid char
2019-12-25 20:38:48 +01:00
Marcin Kościelnicki
a24596def3
iopadmap: Emit tristate buffers with const OE for some edge cases.
2019-12-25 17:37:58 +01:00
Marcin Kościelnicki
13a3041030
Merge pull request #1593 from YosysHQ/mwk/dsp48a1-pmgen
...
xilinx_dsp: Initial DSP48A/DSP48A1 support.
2019-12-25 16:18:44 +01:00
Marcin Kościelnicki
e226a8f7f1
Minor nit fixes
2019-12-25 15:39:40 +01:00
Eddie Hung
2e21aa59a2
Add DSP cascade tests
2019-12-23 14:58:06 -08:00
Eddie Hung
1d0ac659ad
Fix OPMODE for PCIN->PCOUT cascades in xc6s, check B[01]REG too
2019-12-23 14:40:59 -08:00
Eddie Hung
75acaff6f5
Fix CEA/CEB check
2019-12-23 14:22:13 -08:00
Eddie Hung
edabe73377
Fix checking CE[AB] and for direct connections
2019-12-23 13:41:26 -08:00
Eddie Hung
71cac30309
Support unregistered cascades for A and B inputs
2019-12-23 12:38:18 -08:00
Eddie Hung
d00533eaa8
Add DSP48A* PCOUT -> PCIN cascade support
2019-12-23 11:42:46 -08:00
Marcin Kościelnicki
dadaf7ed78
xilinx: Test our DSP48A/DSP48A1 simulation models.
2019-12-23 20:36:43 +01:00
Eddie Hung
509070f82f
Disable clock domain partitioning in Yosys pass, let ABC do it
2019-12-23 08:36:20 -08:00
Eddie Hung
6eadd4390a
write_xaiger to opt instead of just clean whiteboxes
2019-12-23 08:35:53 -08:00
Marcin Kościelnicki
666c6128a9
xilinx_dsp: Initial DSP48A/DSP48A1 support.
2019-12-22 20:51:14 +01:00
Miodrag Milanovic
436fea9e69
Addressed review comments
2019-12-21 20:23:23 +01:00
Miodrag Milanovic
1937091f62
iopad no op for compatibility with old scripts
2019-12-21 13:21:45 +01:00
Miodrag Milanovic
477e43d921
Fix xilinx tests, when iopads are default
2019-12-21 13:18:44 +01:00
Miodrag Milanovic
2fcf683af4
Make iopad option default for all xilinx flows
2019-12-21 11:56:41 +01:00
Eddie Hung
aa1adb0f1e
Merge pull request #1588 from YosysHQ/eddie/xaiger_cleanup
...
write_xaiger: only instantiate each whitebox cell type once
2019-12-20 14:56:08 -08:00
Eddie Hung
d3fc94405f
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-12-20 14:07:23 -08:00
Eddie Hung
5986a4df40
Add abc9_arrival times for RAM{32,64}M
2019-12-20 14:06:59 -08:00
Eddie Hung
1ea1e8e54f
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-12-20 13:56:13 -08:00
Eddie Hung
7928eb113c
Add RAM{32,64}M to abc9_map.v
2019-12-20 13:41:23 -08:00
Eddie Hung
ff2645ce0b
Put specify/endspecify inside ``
2019-12-20 13:38:32 -08:00
Eddie Hung
1482f32d53
Merge pull request #1585 from YosysHQ/eddie/fix_abc9_lut
...
Interpret "abc9 -lut" as lut string only if [0-9:]
2019-12-20 13:09:00 -08:00
Eddie Hung
a75e08c709
write_xaiger: only instantiate each whitebox cell type once
2019-12-20 13:07:24 -08:00
Eddie Hung
e58c3f8351
Merge pull request #1587 from YosysHQ/revert-1558-eddie/xaiger_cleanup
...
Revert "Optimise write_xaiger"
2019-12-20 13:03:48 -08:00
Eddie Hung
f5e0a07ad6
Add $_FF_ and $_SR* courtesy of @mwkmwkmwk
2019-12-20 13:00:04 -08:00
Eddie Hung
d038cea3c7
More stringent check for flop cells
2019-12-20 12:32:00 -08:00
Eddie Hung
10e82e103f
Revert "Optimise write_xaiger"
2019-12-20 12:05:45 -08:00
Graham Edgecombe
319cba70d3
Fix linking with Python 3.8
...
The behaviour of python-config --libs has changed in Python 3.8.
For example, compare the output of it with Python 3.7 and 3.8 on an
ArchLinux system:
$ python3.7-config --libs
-lpython3.7m -lcrypt -lpthread -ldl -lutil -lm
$ python3.8-config --libs
-lcrypt -lpthread -ldl -lutil -lm -lm
$
The lack of -lpython in the latter case causes the linker to fail when
attempting to build Yosys against Python 3.8.
Passing the new --embed flag to python-config adds -lpython, just like
earlier versions of Python:
$ python3.8-config --embed --libs
-lpython3.8 -lcrypt -lpthread -ldl -lutil -lm -lm
$
This commit adds code for automatically detecting support for the
--embed flag. If it is supported, it is passed to all python-config
invocations. This fixes building against Python 3.8.
2019-12-20 10:23:18 +01:00
Graham Edgecombe
2a8cfdebbb
Add PYTHON_CONFIG variable to the Makefile
2019-12-20 10:23:18 +01:00
Eddie Hung
45f0f1486b
Add RAM{32,64}M to abc9_map.v
2019-12-19 11:24:39 -08:00
Eddie Hung
979bf36fb0
Split into $__ABC9_ASYNC[01], do not add cell->type to clkdomain_t
2019-12-19 11:23:41 -08:00
Eddie Hung
94f15f023c
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-12-19 10:29:40 -08:00
Eddie Hung
269ba56a6d
Merge pull request #1581 from YosysHQ/clifford/fix1565
...
Fix sim for assignments with lhs<rhs size
2019-12-19 12:24:27 -05:00
Eddie Hung
df626ee7ab
Merge pull request #1558 from YosysHQ/eddie/xaiger_cleanup
...
Optimise write_xaiger
2019-12-19 12:24:03 -05:00
Eddie Hung
d406f2ffd7
Merge pull request #1569 from YosysHQ/eddie/fix_1531
...
verilog: preserve size of $genval$-s in for loops
2019-12-19 12:21:33 -05:00
Eddie Hung
d675f22f4e
Merge pull request #1571 from YosysHQ/eddie/fix_1570
...
mem_arst.v: do not redeclare ANSI port
2019-12-19 12:21:22 -05:00
Marcin Kościelnicki
8b2c9f4518
xilinx: Add simulation models for remaining CLB primitives.
2019-12-19 18:04:04 +01:00
Marcin Kościelnicki
561ae1c5c4
xilinx_dffopt: Keep order of LUT inputs.
...
See rationale at https://github.com/YosysHQ/yosys/pull/1557#discussion_r359196549
2019-12-19 18:01:43 +01:00
Eddie Hung
76ba06a79e
Bump ABC again
2019-12-18 15:14:38 -08:00
Eddie Hung
3b559de6e9
Interpret "abc9 -lut" as lut string only if [0-9:]
2019-12-18 12:21:12 -08:00
Eddie Hung
f52c6efd9d
Add "scratchpad" to CHANGELOG
2019-12-18 12:09:11 -08:00
Eddie Hung
d0afe4e10d
Merge branch 'master' of github.com:YosysHQ/yosys
2019-12-18 12:08:38 -08:00
David Shah
520f1646cf
Merge pull request #1563 from YosysHQ/dave/async-prld
...
ecp5: Add support for mapping PRLD FFs
2019-12-18 19:42:17 +00:00
