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Code Activity
15959 commits 122 branches 59 tags 73 MiB
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8 commits

Author SHA1 Message Date
YRabbit
79c5a06673 gowin: Fix SDP write enable port. 
This primitive does not have a separate WRE port, so we regulate writing
using Clock Enable.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2024-01-30 17:06:59 +10:00
YRabbit
a5fdf3f881 gowin: Change BYTE ENABLE handling. 
When inferring we allow writing to all bytes for now.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2024-01-27 17:19:49 +10:00
YRabbit
ae991abf2e gowin: fix the BRAM mapping. 
The primitives used have been corrected and changes have been made to the set of signals.
The empirically established need to set the OCEx signal to 1 when using READ_MODE=0 is reflected.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2024-01-19 15:26:37 +10:00
Marcelina Kościelnicka
e4d811561c gowin: Use memory_libmap pass. 2022-05-18 17:32:56 +02:00
Pepijn de Vos
5fad53b504 add 32-bit BRAM and byte-enables 2019-10-28 10:33:27 +01:00
Pepijn de Vos
96efa63f16 fix BRAM width and init 2019-09-06 10:55:04 +02:00
Pepijn de Vos
47374a495d support bram initialisation 2019-09-05 17:25:51 +02:00
Diego
f9272fc56d GoWin enablement: DRAM, initial BRAM, DRAM init, DRAM sim and synth_gowin flow 2019-04-12 23:40:02 -05:00