307 commits

Author	SHA1	Message	Date
Clifford Wolf	0f38008ed3	Added "design" command (-reset, -save, -load)	2013-07-27 14:27:51 +02:00
Clifford Wolf	21e38bed98	Added "eval" pass	2013-06-19 09:30:37 +02:00
Clifford Wolf	6971c4db62	Added RTLIL::Module::fixup_ports() API and RTLIL::*::rewrite_sigspecs() API	2013-06-18 17:11:13 +02:00
Clifford Wolf	21d9251e52	Added "dump" command (part ilang backend)	2013-06-02 17:53:30 +02:00
Clifford Wolf	88af5b6a16	Improved opt_share for reduce cells	2013-03-29 11:19:21 +01:00
Clifford Wolf	041c06bd9d	Create nice errors when calling RTLIL::Module::derive() of base class	2013-03-26 19:27:49 +01:00
Clifford Wolf	7764d0ba1d	initial import	2013-01-05 11:13:26 +01:00