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Author SHA1 Message Date
Adrien Prost-Boucle
62196cbc0a Himbaechel for Xilinx uarch : Improve mapping of multiplexers
- Add explicitly handling of A_WIDTH=1 for completeness
- mux2 uses one LUT3 instead of a hard mux (which did use LUTs anyway)
- mux4 uses one LUT4 instead of hard muxes (which did use LUTs anyway)
- mux8 uses only bottom half of a slice
- Add a mux12 for intermediate variant between mux8 and mux16
- For sizes larger than 16 inputs, instantiate the right mux size
- More comments about implementation choices
- More tests including with -widemux and -abc9, and more comments
2025-06-30 16:46:29 +02:00
Marcelina Kościelnicka
ea79e16bab xilinx_dffopt: Don't crash on missing IS_*_INVERTED.
The presence of IS_*_INVERTED on FD* cells follows Vivado, which
apparently has been decided by a dice roll.  Just assume false if the
parameter doesn't exist.

Fixes #2559.
2021-01-27 00:32:00 +01:00
Marcelina Kościelnicka
aee439360b Add force_downto and force_upto wire attributes.
Fixes #2058.
2020-05-19 01:42:40 +02:00
Miodrag Milanovic
a82c701668 Make test without iopads 2019-12-28 16:22:24 +01:00
Miodrag Milanovic
509da7ed1a Revert "Fix xilinx tests, when iopads are default"
This reverts commit 477e43d921.
2019-12-28 16:12:45 +01:00
Miodrag Milanovic
477e43d921 Fix xilinx tests, when iopads are default 2019-12-21 13:18:44 +01:00
Marcin Kościelnicki
f382164d6e tests/xilinx: fix flaky mux test 2019-12-18 15:53:29 +01:00
Miodrag Milanovic
5603595e5c Share common tests 2019-10-18 12:19:59 +02:00
Miodrag Milanovic
c2ec7ca703 Moved all tests in arch sub directory 2019-10-18 11:06:12 +02:00
Renamed from tests/xilinx/mux.ys (Browse further)