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Author	SHA1	Message	Date
Adrien Prost-Boucle	62196cbc0a	Himbaechel for Xilinx uarch : Improve mapping of multiplexers - Add explicitly handling of A_WIDTH=1 for completeness - mux2 uses one LUT3 instead of a hard mux (which did use LUTs anyway) - mux4 uses one LUT4 instead of hard muxes (which did use LUTs anyway) - mux8 uses only bottom half of a slice - Add a mux12 for intermediate variant between mux8 and mux16 - For sizes larger than 16 inputs, instantiate the right mux size - More comments about implementation choices - More tests including with -widemux and -abc9, and more comments	2025-06-30 16:46:29 +02:00
Miodrag Milanovic	9bd9db56c8	Unify verilog style	2019-10-18 12:50:24 +02:00
Miodrag Milanovic	5603595e5c	Share common tests	2019-10-18 12:19:59 +02:00

Author

SHA1

Message

Date

Adrien Prost-Boucle

62196cbc0a

Himbaechel for Xilinx uarch : Improve mapping of multiplexers

- Add explicitly handling of A_WIDTH=1 for completeness
- mux2 uses one LUT3 instead of a hard mux (which did use LUTs anyway)
- mux4 uses one LUT4 instead of hard muxes (which did use LUTs anyway)
- mux8 uses only bottom half of a slice
- Add a mux12 for intermediate variant between mux8 and mux16
- For sizes larger than 16 inputs, instantiate the right mux size
- More comments about implementation choices
- More tests including with -widemux and -abc9, and more comments

2025-06-30 16:46:29 +02:00

Miodrag Milanovic

9bd9db56c8

Unify verilog style

2019-10-18 12:50:24 +02:00

Miodrag Milanovic

5603595e5c

Share common tests

2019-10-18 12:19:59 +02:00

Renamed from tests/arch/anlogic/mux.v (Browse further)

3 commits