39 commits

Author	SHA1	Message	Date
Clifford Wolf	1e227caf72	Improvements and fixes in autotest.sh script and test_autotb	2016-05-20 16:58:02 +02:00
Kaj Tuomi	f6221ade95	Fix for Modelsim transcript line warp issue #164	2016-05-19 11:34:38 +03:00
Sergey Kvachonok	e14055edf0	Optionally use ${CC} when compiling test utils. ... Default to gcc when not set.	2016-03-25 10:35:42 +03:00
Clifford Wolf	c475deec6c	Switched to Python 3	2015-08-22 09:59:33 +02:00
Larry Doolittle	6c00704a5e	Another block of spelling fixes ... Smaller this time	2015-08-14 23:27:05 +02:00
Clifford Wolf	84bf862f7c	Spell check (by Larry Doolittle)	2015-08-14 10:56:05 +02:00
Clifford Wolf	d58c3eca3a	Some test related fixes ... (incl. removal of three bad test cases)	2015-02-12 17:45:44 +01:00
Clifford Wolf	8d295730e5	Refactoring of memory_bram and xilinx brams	2015-01-18 19:05:29 +01:00
Clifford Wolf	dfa42e272c	Tiny fix in vcdcd.pl	2015-01-13 12:59:29 +01:00
Clifford Wolf	7815f81c32	Added "synth" command	2014-09-14 16:09:06 +02:00
Clifford Wolf	76f8128123	Fixed autotest for non-basename arguments	2014-09-06 12:10:57 +02:00
Clifford Wolf	88db09255b	Added autotest -e (do not use -noexpr on write_verilog)	2014-08-30 18:34:07 +02:00
Clifford Wolf	358bf70a21	Added "wreduce" to some of the standard test benches	2014-08-03 20:22:33 +02:00
Clifford Wolf	03ef9a75c6	Added "test_autotb -n <num_iter>" option	2014-08-01 03:55:51 +02:00
Clifford Wolf	7d98645fe8	Added "make -j{N}" support to "make test"	2014-07-30 19:23:26 +02:00
Clifford Wolf	e6df25bf74	Renamed "write_autotest" to "test_autotb" and moved to passes/tests/	2014-07-29 21:12:50 +02:00
Clifford Wolf	1241a9fd50	Added "opt_const -fine" and "opt_reduce -fine"	2014-07-21 16:34:16 +02:00
Clifford Wolf	ec3a798194	Also simulate unmapped memories in "make test"	2014-07-17 16:53:52 +02:00
Clifford Wolf	964a67ac41	Added note to "make test": use git checkout of iverilog	2014-07-16 10:03:07 +02:00
Clifford Wolf	a67cd2d4a2	Progress in Verific bindings	2014-03-17 01:56:00 +01:00
Clifford Wolf	0ac915a757	Progress in Verific bindings	2014-03-14 11:46:13 +01:00
Clifford Wolf	772330608a	Added vcd2txt.pl and txt2tikztiming.py (tests/tools/...)	2014-02-19 12:40:49 +01:00
Clifford Wolf	30379ea20d	Added frontend (-f) option to autotest.sh	2014-02-15 15:40:17 +01:00
Clifford Wolf	7664f5d92b	Updated ABC and some related changes	2014-02-13 08:07:08 +01:00
Clifford Wolf	9ce7b0fc3b	Disabled "abc -dff" in "make test" for now (waiting for scorr bugfix in ABC)	2014-02-12 13:11:58 +01:00
Clifford Wolf	aa9da46807	Removed old unused files from tests/	2014-02-05 01:55:39 +01:00
Clifford Wolf	de9226a64f	Replaced isim with xsim in tests/tools/autotest.sh, removed xst support	2014-02-03 13:00:55 +01:00
Clifford Wolf	6dec0e0b3e	Added autotest.sh -p option	2014-01-02 17:52:48 +01:00
Clifford Wolf	ab3f6266ad	Use "abc -dff" in "make test"	2013-12-31 21:25:34 +01:00
Clifford Wolf	a582b9d184	Fixed commented out techmap call in tests/tools/autotest.sh	2013-12-31 13:51:25 +01:00
Clifford Wolf	1afe6589df	Renamed stdcells_sim.v to simcells.v and fixed blackbox.v	2013-11-24 20:44:00 +01:00
Clifford Wolf	1e6836933d	Added modelsim support to autotest	2013-11-24 15:10:43 +01:00
Clifford Wolf	288ba9618a	Moved common techlib files to techlibs/common	2013-09-15 11:52:57 +02:00
Clifford Wolf	c8763301b4	Added $div and $mod technology mapping	2013-08-09 17:09:24 +02:00
Clifford Wolf	00a6c1d9a5	Major redesign of expr width/sign detecion (verilog/ast frontend)	2013-07-09 14:31:57 +02:00
Clifford Wolf	ff4a1dd06c	Improved vcdcd.pl (added -d option)	2013-05-14 09:41:47 +02:00
Clifford Wolf	be8ecd6d16	Some improvements in vcdcd.pl	2013-05-14 08:50:59 +02:00
Clifford Wolf	2d9cbd3b02	added more .gitignore files (make test)	2013-01-05 11:35:52 +01:00
Clifford Wolf	7764d0ba1d	initial import	2013-01-05 11:13:26 +01:00