yosys

mirror of https://github.com/YosysHQ/yosys synced 2025-05-22 06:54:03 +00:00

1971 commits 114 branches 54 tags 62 MiB

Author	SHA1	Message	Date
Clifford Wolf	7bde74cd2a	Added more FF types to xilinx/cells.v	2015-01-16 15:24:54 +01:00
Clifford Wolf	b197279f3c	Added Xilinx MUXF7 and MUXF8 support	2015-01-15 13:50:04 +01:00
Clifford Wolf	b64b38eea2	Renamed $lut ports to follow A-Y naming scheme	2014-08-15 14:18:40 +02:00
Clifford Wolf	532091afcb	Added more generic _TECHMAP_ wire mechanism to techmap pass	2013-11-23 15:58:06 +01:00
Clifford Wolf	d635f8adaa	Renamed techlibs/xilinx7 to techlibs/xilinx	2013-10-26 22:29:40 +02:00

Renamed from techlibs/xilinx7/cells.v (Browse further)