377 commits

Author	SHA1	Message	Date
Eddie Hung	0aae3b4f43	Fix techmapping muxes some more	2019-06-24 12:50:48 -07:00
Eddie Hung	2b4501503d	Fix mux techmapping	2019-06-24 12:18:17 -07:00
Eddie Hung	aa1eeda567	Modify costs for muxcover	2019-06-24 11:51:55 -07:00
Eddie Hung	36e6da5396	Change synth_xilinx's -nomux to -minmuxf <int>	2019-06-24 10:04:01 -07:00
Eddie Hung	d54dceb547	Merge remote-tracking branch 'origin/xaig' into xc7mux	2019-06-22 19:44:17 -07:00
Eddie Hung	792d0670c3	Add comment to xc7 box	2019-06-22 14:28:24 -07:00
Eddie Hung	7903ebe3e0	Carry in/out box ordering now move to end, not swap with end	2019-06-22 14:18:42 -07:00
Eddie Hung	65c022c257	Remove DFF and RAMD box info for now	2019-06-21 20:41:14 -07:00
Eddie Hung	bbf3ad90f5	Remove $_MUX4_ techmap rule	2019-06-21 18:12:33 -07:00
Eddie Hung	39e0e006d5	Fix wreduce call (!!!), tweak muxcover costs	2019-06-21 18:12:07 -07:00
Eddie Hung	faa2d6fc1c	Constrain wreduce only if wide mux	2019-06-21 17:12:34 -07:00
Eddie Hung	aeee9dcad7	Simplify and comment out mux_map.v	2019-06-21 17:06:30 -07:00
Eddie Hung	ed00823b41	synth_xilinx to now wreduce except $mux, remove extra peepopt	2019-06-21 16:56:56 -07:00
Eddie Hung	29aee0989f	mux_map to no longer copy last value into 1'bx	2019-06-21 16:55:59 -07:00
Eddie Hung	8bce3fb329	Fix spacing	2019-06-21 16:55:34 -07:00
Eddie Hung	694d40719f	Fix spacing again, A_forward -> A_backward	2019-06-21 16:47:07 -07:00
Eddie Hung	11886c874c	Restore wreduce to synth_xilinx, after muxcover	2019-06-21 16:18:29 -07:00
Eddie Hung	44fc616fc7	Revert B_SIGNED optimisation, since only works for Y_WIDTH==1	2019-06-21 16:18:14 -07:00
Eddie Hung	4d6fac019a	Fix spacing	2019-06-21 16:06:13 -07:00
Eddie Hung	aa0b107afb	synth_xilinx to use _ABC macro, and perform muxpack again	2019-06-21 15:48:20 -07:00
Eddie Hung	9abde12110	Add $__XILINX_MUXF78 to preserve entire box	2019-06-21 15:47:42 -07:00
Eddie Hung	7acbea6b28	Fix alignment	2019-06-21 14:38:30 -07:00
Eddie Hung	f433a52374	Add FIXME about need for -mux4	2019-06-21 11:15:23 -07:00
Eddie Hung	c6b4653ebe	Since muxcover uses MUX4s, blast them back to gates here	2019-06-21 11:13:01 -07:00
Eddie Hung	dd22edcd28	Expand synth -coarse without wreduce, move muxcover	2019-06-21 11:12:32 -07:00
Eddie Hung	f11c9a419b	Call opt_expr -mux_undef to get rid of 1'bx in muxes prior to abc	2019-06-20 17:38:16 -07:00
Eddie Hung	d1dadfcec8	Call opt_expr -mux_undef to get rid of 1'bx in muxes prior to abc	2019-06-20 16:45:09 -07:00
Eddie Hung	9faab38e8d	mux_map to drop sign bit, and eliminate 'bx-es	2019-06-20 16:45:04 -07:00
Eddie Hung	4ca847a217	Merge remote-tracking branch 'origin/xaig' into xc7mux	2019-06-18 11:49:54 -07:00
Eddie Hung	8e0a47fb92	Really permute Xilinx LUT mappings as default LUT6.I5:A6	2019-06-18 11:48:48 -07:00
Eddie Hung	8f5e6d73ff	Revert "Fix (do not) permute LUT inputs, but permute mux selects" ... This reverts commit da3d2eedd2.	2019-06-18 11:35:21 -07:00
Eddie Hung	3d283e69f8	Merge remote-tracking branch 'origin/xaig' into xc7mux	2019-06-18 09:51:28 -07:00
Eddie Hung	da3d2eedd2	Fix (do not) permute LUT inputs, but permute mux selects	2019-06-18 09:49:57 -07:00
Eddie Hung	2b0e28b261	Merge remote-tracking branch 'origin/xaig' into xc7mux	2019-06-17 22:29:34 -07:00
Eddie Hung	608a95eb01	Fix copy-pasta issue	2019-06-17 22:29:22 -07:00
Eddie Hung	59b4e69d16	Merge remote-tracking branch 'origin/xaig' into xc7mux	2019-06-17 22:25:14 -07:00
Eddie Hung	2a35c4ef94	Permute INIT for +/xilinx/lut_map.v	2019-06-17 22:24:35 -07:00
Eddie Hung	75f8b4cf10	Simplify comment	2019-06-17 19:14:41 -07:00
Eddie Hung	9d56c0d525	Merge remote-tracking branch 'origin/xaig' into xc7mux	2019-06-17 18:25:35 -07:00
Eddie Hung	840562943f	Update LUT7/8 delays to take account for [ABC]OUTMUX delay	2019-06-17 17:06:01 -07:00
Eddie Hung	c15ee827f4	Try -W 300	2019-06-17 10:29:06 -07:00
Eddie Hung	1ec450d6bf	Try -W 300	2019-06-16 12:08:03 -07:00
Eddie Hung	842c110357	Merge remote-tracking branch 'origin/xaig' into xc7mux	2019-06-15 05:48:47 -07:00
Eddie Hung	bf312043d4	Fix upper XC7 LUT[78] delays to use I[01] -> O delay not S -> O	2019-06-15 05:45:16 -07:00
Eddie Hung	b63b2a0bd4	Revert "Remove wide mux inference" ... This reverts commit 738fdfe8f5.	2019-06-14 12:50:24 -07:00
Eddie Hung	8fa74287a7	As per @daveshah1 remove async DFF timing from xilinx	2019-06-14 12:43:20 -07:00
Eddie Hung	2e34859a6b	Add XC7_WIRE_DELAY macro to synth_xilinx.cc	2019-06-14 11:38:22 -07:00
Eddie Hung	ba4b4a0088	Update delays based on SymbiFlow/prjxray-db	2019-06-14 11:33:10 -07:00
Eddie Hung	d47ff7ba87	Rename +/xilinx/abc.{box,lut} -> abc_xc7.{box,lut}	2019-06-14 10:51:11 -07:00
Eddie Hung	ee428f73ab	Remove WIP ABC9 flop support	2019-06-14 10:37:52 -07:00