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47 commits

Author SHA1 Message Date
Sean Cross
82f60ba938 Makefile: don't assume python is called python3 
On some architectures, notably on Windows, the official name for the
Python binary from python.org is `python`.  The build system assumes
that python is called `python3`, which breaks under this architecture.

There is already infrastructure in place to determine the name of the
Python binary when building PYOSYS.  Since Python is now always required
to build Yosys, enable this check universally which sets the
`PYTHON_EXECUTABLE` variable.

Then, reuse this variable in other Makefiles as necessary, rather than
hardcoding `python3` everywhere.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-10-19 14:04:52 +08:00
Eddie Hung
aae2b9fd9c Rename abc_* names/attributes to more precisely be abc9_* 2019-10-04 11:04:10 -07:00
Eddie Hung
27167848f4 Revert "Add a xilinx_finalise pass" 
This reverts commit 23d90e0439.
 2019-09-23 19:52:55 -07:00
Eddie Hung
23d90e0439 Add a xilinx_finalise pass 2019-09-23 18:56:02 -07:00
Eddie Hung
fd3b033903 Merge remote-tracking branch 'origin/master' into xc7dsp 2019-09-18 12:23:22 -07:00
Marcin Kościelnicki
09ac36da60 xilinx: Make blackbox library family-dependent. 
Fixes #1246.
 2019-09-15 13:37:24 +02:00
Eddie Hung
feb3fa65a3 Merge remote-tracking branch 'origin/master' into xc7dsp 2019-09-11 00:01:31 -07:00
Marcin Kościelnicki
fda94311ee synth_xilinx: Support init values on Spartan 6 flip-flops properly. 2019-09-07 16:30:43 +02:00
Eddie Hung
e742478e1d Merge remote-tracking branch 'origin/master' into xc7dsp 2019-09-05 13:01:27 -07:00
Eddie Hung
b7a48e3e0f Merge remote-tracking branch 'origin/master' into xc7dsp 2019-08-20 20:18:17 -07:00
Eddie Hung
8f666ebac1 Merge remote-tracking branch 'origin/master' into xaig_dff 2019-08-20 17:36:14 -07:00
Eddie Hung
be9e4f1b67 Use abc_{map,unmap,model}.v 2019-08-20 12:39:11 -07:00
Eddie Hung
24c934f1af Merge branch 'eddie/abc9_refactor' into xaig_dff 2019-08-16 16:51:22 -07:00
Eddie Hung
43616e1414 Update Makefile too 2019-07-18 14:51:55 -07:00
Eddie Hung
5f00d335d4 Oops forgot these files 2019-07-15 15:03:15 -07:00
Marcin Kościelnicki
ce250b341c synth_xilinx: Initial Spartan 6 block RAM inference support. 2019-07-11 14:45:48 +02:00
Eddie Hung
052060f109 Merge remote-tracking branch 'origin/master' into xaig_dff 2019-07-10 16:05:41 -07:00
Eddie Hung
699d8e3939 Merge remote-tracking branch 'origin/master' into xaig_dff 2019-07-01 10:44:42 -07:00
Eddie Hung
62ba724ccb Merge remote-tracking branch 'origin/master' into xc7mux 2019-06-29 19:39:27 -07:00
Eddie Hung
dd8d264bf5 install *_nowide.lut files 2019-06-29 19:37:04 -07:00
Eddie Hung
295bb23ae0 Wrap FDRE with $__ABC_FDRE containing comb 2019-06-15 09:08:56 -07:00
Eddie Hung
b63b2a0bd4 Revert "Remove wide mux inference" 
This reverts commit 738fdfe8f5.
 2019-06-14 12:50:24 -07:00
Eddie Hung
d47ff7ba87 Rename +/xilinx/abc.{box,lut} -> abc_xc7.{box,lut} 2019-06-14 10:51:11 -07:00
Eddie Hung
738fdfe8f5 Remove wide mux inference 2019-06-12 09:20:46 -07:00
Eddie Hung
e260150321 Add mux_map.v for wide mux 2019-06-04 09:51:47 -07:00
Eddie Hung
79fb291dbe Cleanup, call pmux2shiftx even without -nosrl 2019-04-22 12:14:37 -07:00
Eddie Hung
3ac4977b70 Add +/xilinx/cells_box.v containing models for ABC boxes 2019-04-16 11:21:03 -07:00
Eddie Hung
3e368593eb Add cells.lut to techlibs/xilinx/ 2019-04-09 14:33:37 -07:00
Eddie Hung
2ae26b986c Add techlibs/xilinx/cells.box 2019-04-09 10:58:58 -07:00
Keith Rothman
3090951d54 Changes required for VPR place and route synth_xilinx. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-03-01 12:02:27 -08:00
Clifford Wolf
6991c132b5 Add Xilinx RAM64X1D and RAM128X1D simulation models 2018-03-07 17:31:48 +01:00
Clifford Wolf
8a69759306 Add techlibs/xilinx/lut2lut.v 2017-07-10 12:09:05 +02:00
Clifford Wolf
ff5c61b120 Added black box modules for all the 7-series design elements (as listed in ug953) 2016-03-19 11:09:10 +01:00
Clifford Wolf
c475deec6c Switched to Python 3 2015-08-22 09:59:33 +02:00
Clifford Wolf
9596fe74de Another bugfix for ice40 and xilinx brams_init make rules 2015-08-16 21:39:34 +02:00
Clifford Wolf
aedcfd6fd3 Fixed Makefile rules for generated share files 2015-08-16 21:15:07 +02:00
Clifford Wolf
e4ef000b70 Adjust makefiles to work with out-of-tree builds 
This is based on work done by Larry Doolittle
 2015-08-12 15:04:44 +02:00
Clifford Wolf
61512b6f41 Verific build fixes 2015-05-17 08:19:52 +02:00
Clifford Wolf
b00cad81d7 Towards DRAM support in Xilinx flow 2015-04-09 08:17:14 +02:00
Clifford Wolf
8520b7fbe0 Added support for initialized xilinx brams 2015-04-06 17:07:10 +02:00
Clifford Wolf
4389d9306e Added Xilinx bram black-box modules 2015-04-06 08:44:30 +02:00
Clifford Wolf
d29d26f882 Various cleanups in xilinx techlib 2015-01-18 19:43:54 +01:00
Clifford Wolf
7031231145 Added MUXCY and XORCY support to synth_xilinx 2015-01-17 15:39:54 +01:00
Clifford Wolf
1d96277f5d Added add_share_file Makefile macro 2015-01-08 00:23:18 +01:00
Clifford Wolf
8898897f7b Towards Xilinx bram support 2015-01-04 14:23:30 +01:00
Clifford Wolf
b17d6531c8 Added "make PRETTY=1" 2014-07-24 17:15:01 +02:00
Clifford Wolf
4a3669d871 Added synth_xilinx command 2013-10-27 09:51:06 +01:00