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Code Activity
14052 commits 98 branches 53 tags 45 MiB
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14052 commits

Author SHA1 Message Date
Martin Povišer
5f8d7ff170 Start new write_xaiger2 backend for export w/ boxes 2024-09-18 16:55:02 +02:00
Martin Povišer
ea765686b6 aiger2: Adjust hierarchy/port handling 2024-09-18 16:55:02 +02:00
Martin Povišer
2a3e907da8 aiger2: Adjust typing 2024-09-18 16:42:56 +02:00
Martin Povišer
72d65063c3 aiger2: Ignore benign cells 2024-09-18 16:42:56 +02:00
Martin Povišer
1ab7f29933 Start read_xaiger2 -sc_mapping 2024-09-18 16:42:56 +02:00
Martin Povišer
6cecf19ff4 aiger2: Ingest $bmux 2024-09-18 16:42:56 +02:00
Martin Povišer
1cfb9023c4 aiger2: Use REDUCE for reduction ops 2024-09-18 16:42:56 +02:00
Martin Povišer
6c1fa45995 aiger2: Ingest $pmux 2024-09-18 16:42:56 +02:00
Martin Povišer
9db1ca83fc aiger2: Drop empty_lit() as a function 2024-09-17 13:58:07 +02:00
Martin Povišer
dbc937b2a7 aiger2: Describe supported cells in help 2024-09-17 13:55:58 +02:00
Martin Povišer
e4b24e8200 aiger2: Fix literal typing 2024-09-17 13:55:58 +02:00
Martin Povišer
8e29675a23 aiger2: Support $bwmux, comparison operators 2024-09-17 13:55:58 +02:00
Martin Povišer
d7128cb787 aiger2: Use shorthands 2024-09-17 13:55:58 +02:00
Martin Povišer
e59387e5a9 aiger2: Add aigsize as a second user of index 2024-09-17 13:55:58 +02:00
Martin Povišer
de8a2fb936 aiger2: Fix duplicate symbols on multibit ports 2024-09-17 13:55:58 +02:00
Martin Povišer
5671c10173 aiger2: Add strashing option 2024-09-17 13:55:58 +02:00
Martin Povišer
fa39227416 aiger2: Support $pos 2024-09-17 13:55:58 +02:00
Martin Povišer
fb26945a20 Start an 'aiger2' backend 2024-09-17 13:55:58 +02:00
Martin Povišer
4cfdb7ab50 Adjust operation naming in aigmap test 2024-09-17 13:55:58 +02:00
Martin Povišer
a553b7c0c7
Merge pull request from YosysHQ/claire/bufnorm 
Add "buffered-normalized mode", add $buf cell type, and add "bufnorm" command
 2024-09-17 11:27:23 +02:00
Martin Povišer
eeffca9470 simlib: Add $buf disclaimer 2024-09-17 10:46:20 +02:00
Martin Povišer
e13ace675e dump: Update help after option removal 2024-09-17 10:46:20 +02:00
Martin Povišer
38de01807e Mark bufnorm experimental 2024-09-17 10:46:20 +02:00
Martin Povišer
865df26fac Adjust buf-normalized mode 2024-09-17 10:46:20 +02:00
Claire Xenia Wolf
80119386c0 Add RTLIL "buffered-normalized mode" and improve "bufnorm" pass 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2024-09-17 10:46:20 +02:00
Claire Xenia Wolf
8bb70bac8d Improvements in "bufnorm" pass 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2024-09-17 10:46:20 +02:00
Claire Xenia Wolf
d027ead4b5 Improvements in "bufnorm" pass 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2024-09-17 10:46:20 +02:00
Claire Xenia Wolf
4d469f461b Add coarse-grain $buf buffer cell type 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2024-09-17 10:46:20 +02:00
Claire Xenia Wolf
f4b7ea5fb3 Improvements in "bufnorm" pass 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2024-09-17 10:46:20 +02:00
Claire Xenia Wolf
32808a0393 Improvements and fixes to "bufnorm" cmd 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2024-09-17 10:46:20 +02:00
Claire Xenia Wolf
d0b5dfa6ef Add bufnorm pass 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2024-09-17 10:46:20 +02:00
github-actions[bot]
c8846243c2 Bump version 2024-09-17 00:16:41 +00:00
Emil J
f8ad371254
Merge pull request from yrabbit/cpu-wip 
Gowin. Add the EMCU primitive.
 2024-09-16 15:41:14 +02:00
Emil J
52382c6544
Merge pull request from YosysHQ/emil/clock_gate 
clockgate: centralize clock enables out of FFs
 2024-09-16 15:41:01 +02:00
Emil J. Tywoniak
f193bcf683 clockgate: help string 2024-09-16 14:20:33 +02:00
Emil J. Tywoniak
be7c93ec6d clockgate: 1-bit const 0 2024-09-16 13:58:27 +02:00
Emil J
a8a92d3469
clockgate: help string 
Co-authored-by: Martin Povišer <povik@cutebit.org>
 2024-09-16 13:55:53 +02:00
N. Engelhardt
c8b42b7d48
Merge pull request from RCoeurjoly/verific_bounds 2024-09-12 13:04:04 +02:00
github-actions[bot]
229d1ea937 Bump version 2024-09-12 00:19:38 +00:00
Emil J. Tywoniak
1e999a3cb7 clockgate: EN can be a bit on a multi-bit wire 2024-09-11 19:18:25 +02:00
Martin Povišer
34572708d5
Merge pull request from YosysHQ/emil/internal_stats-astnode 
internal_stats: astnode (sizeof)
 2024-09-11 12:21:29 +02:00
Emil J. Tywoniak
1372c47036 internal_stats: astnode (sizeof) 2024-09-11 11:34:20 +02:00
Emil J. Tywoniak
8b464341c2 clockgate: no initvals 2024-09-11 10:24:48 +02:00
YRabbit
ab35dff702 Gowin. Add the EMCU primitive. 
EMCU is a micro-processor based on ARM Cortex-M3 embedded in the
GW1NSR-4C chip used in the Tangnano4k board.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2024-09-11 10:18:51 +10:00
Roland Coeurjoly
bdc43c6592 Add left and right bound properties to wire. Add test. Fix printing 
for signed attributes

Co-authored-by: N. Engelhardt <nak@yosyshq.com>
Co-authored-by: Roland Coeurjoly <rolandcoeurjoly@gmail.com>
 2024-09-10 12:52:42 +02:00
github-actions[bot]
6937241012 Bump version 2024-09-10 00:19:34 +00:00
Emil J. Tywoniak
7e473299bd clockgate: bail on constant signals 2024-09-09 21:20:19 +02:00
Emil J. Tywoniak
dc039d8be4 clockgate: test fine-grained cells 2024-09-09 21:03:22 +02:00
Emil J. Tywoniak
e64fceef70 clockgate: prototype clock gating 2024-09-09 15:00:54 +02:00
Martin Povišer
982fade0df
Merge pull request from hnpl/main 
Initialize area stats in stat pass
 2024-09-09 07:47:08 +02:00