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Author SHA1 Message Date
whitequark
10c3214e56
Merge pull request #2871 from whitequark/cxxrtl-fix-2540-2841 
cxxrtl: don't mark buffered internal wires as UNUSED for debug
 2021-07-16 08:33:30 +00:00
whitequark
44a3d924ce cxxrtl: don't mark buffered internal wires as UNUSED for debug. 
Public wires may alias buffered internal wires, so keep BUFFERED
wires in debug information even if they are private. Debug items are
only created for public wires, so this does not otherwise affect how
debug information is emitted.

Fixes #2540.
Fixes #2841.
 2021-07-16 07:54:49 +00:00
whitequark
c17e385e35
Merge pull request #2870 from whitequark/cxxrtl-fix-2739 
cxxrtl: mark dead local wires as unused even with inlining disabled
 2021-07-16 00:13:16 +00:00
whitequark
54b6cb645f cxxrtl: mark dead local wires as unused even with inlining disabled. 
Fixes #2739.
 2021-07-15 22:27:27 +00:00
Zachary Snow
a9c8ca21d5 sv: fix two struct access bugs 
- preserve signedness of struct members
- fix initial width detection of struct members (e.g., in case expressions)
 2021-07-15 11:57:20 -04:00
Rupert Swarbrick
1aab608cff Add a test for interfaces on modules loaded on-demand 2021-07-14 22:54:50 -04:00
Rupert Swarbrick
7d50b83322 Extract missing module support in hierarchy.cc to a helper function 
I think the code is now a bit easier to follow (and has lost some
levels of indentation!).

The only non-trivial change is that I removed the check for
cell->type[0] != '$' when deciding whether to complain if we couldn't
find a module. This will always be true because of the early exit
earlier in the function.
 2021-07-14 22:54:50 -04:00
whitequark
9008b87c39
Merge pull request #2866 from rswarbrick/found-init 
Delete unused found_init variable
 2021-07-14 12:00:30 +00:00
Rupert Swarbrick
88f20fa4dd Delete unused found_init variable 
Spotted during compilation:

    passes/proc/proc_init.cc: In function ‘void {anonymous}::proc_init(Yosys::RTLIL::Module*, Yosys::SigMap&, Yosys::RTLIL::Process*)’:
    passes/proc/proc_init.cc:31:7: warning: variable ‘found_init’ set but not used [-Wunused-but-set-variable]
 2021-07-14 10:19:07 +01:00
Marcelina Kościelnicka
8bf9cb407d kernel/mem: Add a coalesce_inits helper. 
While this helper is already useful to squash sequential initializations
into one in cxxrtl, its main purpose is to squash overlapping masked memory
initializations (when they land) and avoid having to deal with them in
cxxrtl runtime.
 2021-07-13 15:59:11 +02:00
GCHQDeveloper560
4379375d89 Add support for the Bitwuzla solver 2021-07-12 22:07:58 +02:00
Marcelina Kościelnicka
0565c642a0 kernel/mem: Use delayed removal for inits as well. 2021-07-12 18:28:20 +02:00
Marcelina Kościelnicka
6d7d9ab077 kernel/mem: Add documentation for more helper functions. 2021-07-12 18:28:08 +02:00
Marcelina Kościelnicka
37506d737c cxxrtl: Support memory writes in processes. 2021-07-12 18:27:48 +02:00
Marcelina Kościelnicka
af7fa62251 cxxrtl: Add support for memory read port reset. 2021-07-12 18:27:48 +02:00
Marcelina Kościelnicka
be5cf29699 cxxrtl: Add support for mem read port initial data. 2021-07-12 18:27:48 +02:00
Marcelina Kościelnicka
d5c9595668 cxxrtl: Convert to Mem helpers. 
This *only* does conversion, but doesn't add any new functionality —
support for memory read port init/reset is still upcoming.
 2021-07-12 18:27:48 +02:00
Marcelina Kościelnicka
7f12820b26 kernel/mem: Commit new values of attributes in emit. 2021-07-12 13:39:31 +02:00
Marcelina Kościelnicka
c86a79bf0b kernel/mem: Make the Mem helpers inherit from AttrObject. 2021-07-12 02:51:08 +02:00
Marcelina Kościelnicka
009940f56c rtlil: Make Process handling more uniform with Cell and Wire. 
- add a backlink to module from Process
- make constructor and destructor protected, expose Module functions
  to add and remove processes
 2021-07-12 00:47:34 +02:00
Marcelina Kościelnicka
726fabd65e ice40: Fix LUT input indices in opt_lut -dlogic (again). 
Fixes #2061.
 2021-07-10 21:30:01 +02:00
Miodrag Milanovic
7a5ac90985 Update to latest Verific with extensions for initial assertions 2021-07-09 09:02:27 +02:00
Zachary Snow
4446cfa524 sv: fix a few struct and enum memory leaks 2021-07-06 12:15:08 -04:00
gatecat
2b8f1633ce ecp5: Add DCSC blackbox 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-07-06 14:07:20 +01:00
Claire Xen
676c544abe
Merge pull request #2835 from YosysHQ/verific_command 
Support command files in Verific
 2021-07-05 16:59:37 +02:00
Xiretza
75e5500d4d Makefile: allow running multiple sanitizers at once 2021-07-05 16:42:10 +02:00
Xiretza
a189284a28 Makefile: use git/make -C instead of cd 2021-07-05 16:42:01 +02:00
Xiretza
ef68c2762c Makefile: pass PRETTY=0 to ABC 2021-07-05 16:40:48 +02:00
Xiretza
9c31ecfab8 Makefile: don't bake DESTDIR into libyosys DT_SONAME 
DESTDIR is only used as a temporary destination for installed files
before they are packaged into an archive; the "real" installed location
is determined by PREFIX/{BIN,LIB,DAT}DIR.
 2021-07-05 16:39:16 +02:00
Xiretza
18f4ae482c Makefile: clean up PYOSYS configuration 2021-07-05 16:38:58 +02:00
Miodrag Milanovic
0dbb05a75e Add additional help 2021-07-05 09:16:54 +02:00
whitequark
862e84eb3d
Merge pull request #2842 from whitequark/fix-wasi-build 
Fix WASI build after commit 1d88bea1
 2021-06-19 12:10:29 +00:00
whitequark
02b4e67549 Fix WASI build after commit 1d88bea1. 2021-06-19 02:59:57 +00:00
Miodrag Milanović
5a73f296c9
Merge pull request #2836 from YosysHQ/gatecat/pyosys-sigint 
pyosys: Clear SIGINT handler after Python loads
 2021-06-18 12:07:50 +02:00
Rupert Swarbrick
e2c9580024 Move interface expansion in hierarchy.cc into a helper class 
There should be no functional change, but this splits up the control
flow across functions, using class fields to hold the state that's
being tracked. The result should be a bit easier to read.

This is part of work to add bind support, but I'm doing some
refactoring in the hierarchy pass to make the code a bit easier to
work with. The idea is that (eventually) the IFExpander object will
hold all the logic for expanding interfaces, and then other code can
do bind insertion.
 2021-06-16 21:48:18 -04:00
Zachary Snow
f2c2d73f36 sv: fix up end label checking 
- disallow [gen]blocks with an end label but not begin label
- check validity of module end label
- fix memory leak of package name and end label
- fix memory leak of module end label
 2021-06-16 21:48:05 -04:00
Ashton Snelgrove
092f0cb01e Include blif reader header in public facing extension header files. 2021-06-16 22:29:34 +02:00
gatecat
1d88bea18b pyosys: Clear SIGINT handler after Python loads 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-16 12:34:36 +01:00
Miodrag Milanovic
c0d8da20d5 Support command files in Verific 2021-06-16 11:21:44 +02:00
Xiretza
c6681508f1 verilog: fix leaking of type names in parser 2021-06-14 13:56:51 -04:00
Xiretza
b57e47fad8 verilog: fix wildcard port connections leaking memory 2021-06-14 13:56:51 -04:00
Xiretza
62a42c317c ast: delete wires and localparams after finishing const evaluation 2021-06-14 13:56:51 -04:00
Xiretza
091295a5a5 verilog: fix leaking ASTNodes 2021-06-14 13:56:51 -04:00
Xiretza
9ca5a91724 ast: fix error condition causing assert to fail 
type2str returns a string that doesn't start with $ or \, so it can't be
assigned to an IdString.
 2021-06-14 13:56:51 -04:00
Zachary Snow
b516c681fe macos: fix leak in proc_self_dirname() 2021-06-14 12:33:26 -04:00
Rupert Swarbrick
081111714e Simplify some RTLIL destructors 
No change in behaviour, but use range-based for loops instead of
iterators.
 2021-06-14 12:06:08 -04:00
Marcelina Kościelnicka
801ecc0e1d verilog: Squash a memory leak. 
That was added in ecc22f7fed
 2021-06-14 17:07:41 +02:00
Marcelina Kościelnicka
438bcc68c0 Add regression test for #2824. 2021-06-11 12:06:35 +01:00
gatecat
6a6d049f1c opt_muxtree: Update port_off and port_idx even for constant bits 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-11 12:06:35 +01:00
Marcelina Kościelnicka
1667ad658b opt_expr: Fix mul/div/mod by POT patterns to support >= 32 bits. 
The previous code, in addition to being needlessly limitted to 32 bits
in the first place, also had UB for the 31th bit (doing 1 << 31).
 2021-06-09 19:53:44 +02:00