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Code Activity
10789 commits 114 branches 54 tags 63 MiB
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306 commits

Author SHA1 Message Date
Benedikt Tutzer
95d65971f3 added some checks if python is enabled to make sure everything compiles if python is disabled in the makefile 2018-08-20 16:04:43 +02:00
Benedikt Tutzer
bf7b73acfc Added Wrappers for: 
-IdString
-Const
-CaseRule
-SwitchRule
-SyncRule
-Process
-SigChunk
-SigBit
-SigSpec
With all their member functions as well as the remaining member
functions for Cell, Wire, Module and Design and static functions of
rtlil.h
 2018-08-13 15:18:46 +02:00
Henner Zeller
3aa4484a3c Consistent use of 'override' for virtual methods in derived classes. 
o Not all derived methods were marked 'override', but it is a great
  feature of C++11 that we should make use of.
o While at it: touched header files got a -*- c++ -*- for emacs to
  provide support for that language.
o use YS_OVERRIDE for all override keywords (though we should probably
  use the plain keyword going forward now that C++11 is established)
 2018-07-20 23:51:06 -07:00
Benedikt Tutzer
e7d3f3cd46 added destructors for wires and cells 2018-07-10 08:52:36 +02:00
Benedikt Tutzer
8ebaeecd83 multiple designs can now exist independent from each other. Cells/Wires/Modules can now move to a different parent without referencing issues 2018-07-09 15:48:06 +02:00
Clifford Wolf
eb67a7532b Add $allconst and $allseq cell types 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-02-23 13:14:47 +01:00
Clifford Wolf
c80315cea4 Bugfix in hierarchy handling of blackbox module ports 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-01-05 13:28:45 +01:00
Clifford Wolf
76afff7ef6 Add RTLIL::Const::is_fully_ones() 2017-12-14 02:06:39 +01:00
Clifford Wolf
96ad688849 Add SigSpec::is_fully_ones() 2017-12-14 01:29:09 +01:00
Clifford Wolf
13eb47c692 Add src arguments to all cell creator helper functions 2017-09-09 10:16:48 +02:00
Jason Lowdermilk
71d43cfc08 Merge remote-tracking branch 'upstream/master' 2017-08-30 11:47:06 -06:00
Clifford Wolf
8530333439 Add {get,set}_src_attribute() methods on RTLIL::AttrObject 2017-08-30 11:39:11 +02:00
Jason Lowdermilk
32c0f1193e Add support for source line tracking through synthesis phase 2017-08-29 14:46:35 -06:00
Clifford Wolf
4ba5bd12c6 Add Const methods is_fully_zero(), is_fully_def(), and is_fully_undef() 2017-08-18 11:40:08 +02:00
Clifford Wolf
05df3dbee4 Add "setundef -anyseq" 2017-05-28 11:59:05 +02:00
Clifford Wolf
6934b862d3 Add missing AndnotGate() and OrnotGate() declarations to rtlil.h 2017-05-17 19:10:57 +02:00
Clifford Wolf
05cdd58c8d Add $_ANDNOT_ and $_ORNOT_ gates 2017-05-17 09:08:29 +02:00
Clifford Wolf
5f1d0b1024 Add $live and $fair cell types, add support for s_eventually keyword 2017-02-25 10:36:39 +01:00
Clifford Wolf
3928482a3c Add $cover cell type and SVA cover() support 2017-02-04 14:14:26 +01:00
Clifford Wolf
a926a6afc2 Remember global declarations and defines accross read_verilog calls 2016-11-15 12:42:43 +01:00
Clifford Wolf
bdc316db50 Added $anyseq cell type 2016-10-14 15:24:03 +02:00
Clifford Wolf
53655d173b Added $global_clock verilog syntax support for creating $ff cells 2016-10-14 12:33:56 +02:00
Clifford Wolf
8ebba8a35f Added $ff and $_FF_ cell types 2016-10-12 01:18:39 +02:00
Clifford Wolf
cb7dbf4070 Improvements in assertpmux 2016-09-07 12:42:16 +02:00
Clifford Wolf
eae390ae17 Removed $predict again 2016-08-28 21:35:33 +02:00
Clifford Wolf
721f1f5ecf Added basic support for $expect cells 2016-07-13 16:56:17 +02:00
Ruben Undheim
a8200a773f A few modifications after pull request comments 
- Renamed Design::packages to Design::verilog_packages
- No need to include ast.h in rtlil.h
 2016-06-18 14:23:38 +02:00
Ruben Undheim
178ff3e7f6 Added support for SystemVerilog packages with localparam definitions 2016-06-18 10:53:55 +02:00
Clifford Wolf
ba407da187 Added addBufGate module method 2016-02-02 11:26:07 +01:00
Clifford Wolf
5462399c88 Meaningless coding style change 2016-01-31 16:12:35 +01:00
Rick Altherr
12ebdef17c rtlil: duplicate remove2() for std::set<> 2016-01-29 23:06:40 -08:00
Rick Altherr
9e26147ccd rtlil: change IdString comparison operators to take references instead of copies 2016-01-29 23:06:40 -08:00
Clifford Wolf
6459e3ac39 Removed dangling ';' in rtlil.h 2015-11-26 18:11:34 +01:00
Clifford Wolf
7f110e7018 renamed SigSpec::to_single_sigbit() to SigSpec::as_bit(), added is_bit() 2015-10-24 22:56:40 +02:00
Clifford Wolf
d212d4d0c1 Cosmetic fix in Module::addLut() 2015-09-18 21:55:12 +02:00
Clifford Wolf
ff50bc2ac3 Added $tribuf and $_TBUF_ cell types 2015-08-16 12:54:52 +02:00
Clifford Wolf
84bf862f7c Spell check (by Larry Doolittle) 2015-08-14 10:56:05 +02:00
Clifford Wolf
6c84341f22 Fixed trailing whitespaces 2015-07-02 11:14:30 +02:00
Clifford Wolf
caa274ada6 Added design->rename(module, new_name) 2015-06-30 01:37:59 +02:00
Clifford Wolf
99100f367d Added "rename -top new_name" 2015-06-17 09:38:56 +02:00
Clifford Wolf
f483dce7c2 Added $eq/$neq -> $logic_not/$reduce_bool optimization 2015-04-29 07:28:15 +02:00
Clifford Wolf
49859393bb Improved attributes API and handling of "src" attributes 2015-04-24 22:04:05 +02:00
Clifford Wolf
169d1c4711 Added support for initialized brams 2015-04-06 17:06:15 +02:00
Clifford Wolf
c52a4cdeed Added "dffinit", Support for initialized Xilinx DFF 2015-04-04 19:00:15 +02:00
Clifford Wolf
9ae21263f0 Some cleanups in "clean" 2015-02-24 22:31:30 +01:00
Clifford Wolf
05d4223fb6 Added SigSpec::has_const() 2015-02-08 00:01:51 +01:00
Clifford Wolf
dce1fae777 Added cell->known(), cell->input(portname), cell->output(portname) 2015-02-07 11:40:19 +01:00
Clifford Wolf
f80f5b721d Added "equiv_make -blacklist <file> -encfile <file>" 2015-01-31 12:08:20 +01:00
Clifford Wolf
cb9d0a414d Synced RTLIL::unescape_id() to log_id() behavior 2015-01-30 22:51:16 +01:00
Clifford Wolf
43951099cf Added dict/pool.sort() 2015-01-24 00:13:27 +01:00