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Author	SHA1	Message	Date
Clifford Wolf	0256105ac2	Set version number to 0.1.0+	2013-11-27 06:29:13 +01:00
Clifford Wolf	bc3cc88719	Started implementing undef support in "sat" command	2013-11-25 21:40:00 +01:00
Clifford Wolf	3d95047ce2	Bugfixes in new "stat" command	2013-11-25 21:08:34 +01:00
Clifford Wolf	4c7d6e63ec	Added "stat" command	2013-11-25 20:43:57 +01:00
Clifford Wolf	61412d167f	Improvements in satgen undef handling	2013-11-25 16:50:45 +01:00
Clifford Wolf	bd65e67d8a	Improvements in satgen undef handling	2013-11-25 15:12:01 +01:00
Clifford Wolf	11e8118589	Added ezsat vec_const() api	2013-11-25 15:10:32 +01:00
Clifford Wolf	8c3f4b3957	Started implementing undef handling in satgen	2013-11-25 04:51:33 +01:00
Clifford Wolf	4d43331748	Removed undef feature from ezsat api	2013-11-25 02:50:34 +01:00
Clifford Wolf	76f7c10cfc	Using simplemap mappers from techmap	2013-11-24 23:31:14 +01:00
Clifford Wolf	3ee33cbdaf	Added simplemap pass	2013-11-24 22:52:30 +01:00
Clifford Wolf	1afe6589df	Renamed stdcells_sim.v to simcells.v and fixed blackbox.v	2013-11-24 20:44:00 +01:00
Clifford Wolf	8dafecd34d	Added module->avail_parameters (for advanced techmap features)	2013-11-24 20:29:07 +01:00
Clifford Wolf	4011d47646	Added techmap -D and -I options	2013-11-24 20:04:48 +01:00
Clifford Wolf	7d9a90396d	Added verilog frontend -ignore_redef option	2013-11-24 19:57:42 +01:00
Clifford Wolf	20175afd29	Added "techmap -share_map" option	2013-11-24 19:50:25 +01:00
Clifford Wolf	019b301541	Early wire/reg/parameter width calculation in ast/simplify	2013-11-24 19:40:23 +01:00
Clifford Wolf	620b7c900a	Updated TODOs	2013-11-24 17:58:05 +01:00
Clifford Wolf	ae798d3fd5	Fixed xilinx/example_sim_counter test bench	2013-11-24 17:55:46 +01:00
Clifford Wolf	41205afc39	Added proper dumping of signed/unsigned parameters to verilog backend	2013-11-24 17:47:22 +01:00
Clifford Wolf	0ef22c7609	Added support for signed parameters in ilang	2013-11-24 17:37:27 +01:00
Clifford Wolf	7eaad2218d	Removed now obsolete test cases	2013-11-24 17:30:04 +01:00
Clifford Wolf	f71e27dbf1	Remove auto_wire framework (smarter than the verilog standard)	2013-11-24 17:29:11 +01:00
Clifford Wolf	609caa23b5	Implemented correct handling of signed module parameters	2013-11-24 17:17:21 +01:00
Clifford Wolf	1e6836933d	Added modelsim support to autotest	2013-11-24 15:10:43 +01:00
Clifford Wolf	72b35e0b99	Fixed "flatten" top-module detection: Only use on fully selected designs	2013-11-24 14:10:46 +01:00
Clifford Wolf	981677cf09	Fixed "make install" dependencies	2013-11-24 05:05:50 +01:00
Clifford Wolf	28093d9dd2	Added "top" attribute to mark top module in hierarchy	2013-11-24 05:03:43 +01:00
Clifford Wolf	a4edecb0ca	Updated command-reference-manual.tex	2013-11-23 20:09:47 +01:00
Clifford Wolf	db8ce0fe95	AppNote 010 typo fixes and corrections	2013-11-23 20:04:51 +01:00
Clifford Wolf	e216e0e291	AppNote 010 progress	2013-11-23 18:52:41 +01:00
Clifford Wolf	5f9c7fc6ea	Improved handling of techmap special wires	2013-11-23 16:49:58 +01:00
Clifford Wolf	1de12e1efc	Improved handling of initialized registers	2013-11-23 16:26:59 +01:00
Clifford Wolf	532091afcb	Added more generic _TECHMAP_ wire mechanism to techmap pass	2013-11-23 15:58:06 +01:00
Clifford Wolf	9ab850e45e	Making prograss on Appnote 010	2013-11-23 05:46:51 +01:00
Clifford Wolf	3c023054bc	Progress on AppNote 010	2013-11-22 19:08:29 +01:00
Clifford Wolf	bf501b9ba3	Started to write on AppNote 010: Verilog to BLIF	2013-11-22 17:33:59 +01:00
Clifford Wolf	7b9ca46f8d	Updated command-reference-manual.tex	2013-11-22 15:02:40 +01:00
Clifford Wolf	295e352ba6	Renamed "placeholder" to "blackbox"	2013-11-22 15:01:12 +01:00
Clifford Wolf	c854ad2e7e	Some driver changes/fixes	2013-11-22 14:53:57 +01:00
Clifford Wolf	a362fd81ae	Fixed O(n^2) performance bug in verilog preprocessor	2013-11-22 14:08:43 +01:00
Clifford Wolf	058ceda6a0	Added more performance measurement infrastructure	2013-11-22 14:08:10 +01:00
Clifford Wolf	e4429c480e	Enable {* .. *} feature per default (removes dependency to REJECT feature in flex)	2013-11-22 12:46:02 +01:00
Clifford Wolf	18d003254c	Massive performance improvement from refactoring RTLIL::SigSpec::optimize()	2013-11-22 04:41:20 +01:00
Clifford Wolf	8e58bb330d	Added SigBit struct and refactored RTLIL::SigSpec::extract	2013-11-22 04:07:13 +01:00
Clifford Wolf	7b01ba384f	Improved make rules for profiling and debugging	2013-11-22 04:05:30 +01:00
Clifford Wolf	1c4a6411af	Updated abc	2013-11-21 22:39:10 +01:00
Clifford Wolf	40d9542647	Implemented $_DFFSR_ expression generator in verilog backend	2013-11-21 21:52:30 +01:00
Clifford Wolf	95c94a02fc	Fixed async proc detection in mem2reg	2013-11-21 21:26:56 +01:00
Clifford Wolf	09471846c5	Major improvements in mem2reg and added "init" sync rules	2013-11-21 13:49:00 +01:00