3834 commits

Author	SHA1	Message	Date
Eddie Hung	d3a212ff91	opt_expr to trim A port of $shiftx if Y_WIDTH == 1	2019-08-21 21:53:55 -07:00
Eddie Hung	7d02d17b16	Reuse var	2019-08-21 19:18:40 -07:00
Eddie Hung	5c8344363f	Revert "Trim shiftx_width when upper bits are 1'bx" ... This reverts commit 7e7965ca7b.	2019-08-21 19:18:27 -07:00
Eddie Hung	c7859531c2	opt_expr to trim A port of $shiftx if Y_WIDTH == 1	2019-08-21 19:18:05 -07:00
Eddie Hung	7e7965ca7b	Trim shiftx_width when upper bits are 1'bx	2019-08-21 18:43:17 -07:00
Eddie Hung	ed7be3e6b6	Add comment	2019-08-21 17:36:38 -07:00
Eddie Hung	15188033da	Add variable length support to xilinx_srl	2019-08-21 17:34:40 -07:00
Eddie Hung	6d76ae4c65	Rename pattern to fixed	2019-08-21 15:46:58 -07:00
Eddie Hung	b0a3b430bf	attribute -> attr	2019-08-21 15:44:07 -07:00
Eddie Hung	61b4d7ae13	Use Cell::has_keep_attribute()	2019-08-21 15:41:46 -07:00
Eddie Hung	6fa9e03e4c	xilinx_srl to support FDRE and FDRE_1	2019-08-21 15:35:29 -07:00
Eddie Hung	3c8e8521a6	Fix polarity of EN_POL	2019-08-21 14:42:11 -07:00
Eddie Hung	a980f0d4be	Add CLKPOL == 0	2019-08-21 14:35:40 -07:00
Eddie Hung	1c7d721558	Reject if not minlen from inside pattern matcher	2019-08-21 14:26:24 -07:00
Eddie Hung	cab2bd083e	Get wire via SigBit	2019-08-21 13:47:47 -07:00
Eddie Hung	52fea5b658	Respect \keep on cells or wires	2019-08-21 13:42:03 -07:00
Eddie Hung	5ce0c31d0e	Add init support	2019-08-21 13:05:10 -07:00
Eddie Hung	df53fe12e7	Fix spacing	2019-08-21 12:54:11 -07:00
Eddie Hung	0250712486	Initial progress on xilinx_srl	2019-08-21 12:50:49 -07:00
Eddie Hung	8f69be9cc7	Merge remote-tracking branch 'origin/master' into xaig_arrival	2019-08-21 11:39:14 -07:00
Miodrag Milanovic	948b6f91a1	Fix test_pmgen deps	2019-08-21 17:00:24 +02:00
Clifford Wolf	7d8db1c053	Merge pull request #1314 from YosysHQ/eddie/fix_techmap ... techmap -max_iter to apply to each module individually	2019-08-21 09:12:56 +02:00
Eddie Hung	4cc74346f1	Fix compile error	2019-08-20 20:27:05 -07:00
Eddie Hung	9b9d759451	Fix copy-paste typo	2019-08-20 20:18:51 -07:00
Eddie Hung	b7a48e3e0f	Merge remote-tracking branch 'origin/master' into xc7dsp	2019-08-20 20:18:17 -07:00
Eddie Hung	affe9c9c1a	Merge branch 'eddie/fix_techmap' into xaig_arrival	2019-08-20 20:06:47 -07:00
Eddie Hung	fe61dcce8b	Grammar	2019-08-20 20:05:51 -07:00
Eddie Hung	193eae0c84	techmap -max_iter to apply to each module individually	2019-08-20 19:50:20 -07:00
Eddie Hung	57493e328a	techmap -max_iter to apply to each module individually	2019-08-20 19:48:16 -07:00
Eddie Hung	f1a206ba03	Revert "Remove sequential extension" ... This reverts commit 091bf4a18b.	2019-08-20 18:17:14 -07:00
Eddie Hung	091bf4a18b	Remove sequential extension	2019-08-20 18:16:37 -07:00
Eddie Hung	fad15d276d	retime_mode -> dff_mode	2019-08-20 18:08:58 -07:00
Eddie Hung	505d062daf	Fix use of {CLK,EN}_POLARITY, also add a FIXME	2019-08-20 13:33:31 -07:00
Eddie Hung	c4d4c6db3f	Merge remote-tracking branch 'origin/master' into xaig_dff	2019-08-20 12:00:12 -07:00
Eddie Hung	14c03861b6	Merge pull request #1304 from YosysHQ/eddie/abc9_refactor ... Refactor abc9 to use port attributes, not module attributes	2019-08-20 11:59:31 -07:00
Clifford Wolf	d0117d7d12	Merge branch 'master' into clifford/pmgen	2019-08-20 11:39:23 +02:00
whitequark	749ff864aa	Merge pull request #1309 from whitequark/proc_clean-fix-1268 ... proc_clean: fix order of switch insertion	2019-08-20 00:45:41 +00:00
Eddie Hung	1f03154a0c	Merge remote-tracking branch 'origin/master' into xaig_dff	2019-08-19 15:19:32 -07:00
Eddie Hung	e29df7d5fa	Remove debug	2019-08-19 12:44:43 -07:00
Eddie Hung	91687d3fea	Add (* abc_arrival *) attribute	2019-08-19 12:33:24 -07:00
Eddie Hung	ba2261e21a	Move from cell attr to module attr	2019-08-19 11:18:33 -07:00
Eddie Hung	7e010834eb	Fix typo	2019-08-19 10:41:18 -07:00
Eddie Hung	f42ba811b6	ID({A,B,Y}) -> ID::{A,B,Y} for opt_share.cc	2019-08-19 10:11:47 -07:00
Eddie Hung	2f4e0a5388	Merge remote-tracking branch 'origin/master' into xaig_dff	2019-08-19 10:07:27 -07:00
Eddie Hung	d81a090d89	Unify abc_carry_{in,out} into abc_carry and use port dir, as @mithro	2019-08-19 09:56:17 -07:00
Eddie Hung	e301440a0b	Use attributes instead of params	2019-08-19 09:51:49 -07:00
whitequark	4a942ba7b9	proc_clean: fix order of switch insertion. ... Fixes #1268.	2019-08-19 16:44:23 +00:00
Eddie Hung	9bfe924e17	Set abc_flop and use it in toposort	2019-08-19 09:40:01 -07:00
Clifford Wolf	1e3dd0a2da	Merge branch 'master' of github.com:YosysHQ/yosys into clifford/pmgen	2019-08-19 13:04:06 +02:00
Miodrag Milanovic	dbe3cb9708	Ignore all generated headers for pmgen pass	2019-08-18 10:49:17 +02:00