4 commits

Author	SHA1	Message	Date
Miodrag Milanovic	a689342207	Remove trailing whitespaces	2026-06-23 07:24:59 +02:00
Miodrag Milanovic	48a3dcc02a	End of file fix	2026-06-23 07:23:41 +02:00
Tony Min	d41688f7d7	Revisions (#4) ... * area should be 1 for all LUTs * clean up macros * add log_assert to fail noisily when encountering oddly configured DFF * clean help msg * flatten set to true by default * update * merge mult tests * remove redundant test * move all dsp tests to single file and remove redundant tests * update ram tests * add more dff tests * fix c++20 compile errors * add option to dump verilog * default to use abc9 * remove -abc9 option since its the default now --------- Co-authored-by: tony <minchunlin@gmail.com>	2024-07-08 10:57:16 -04:00
chunlin min	8e7ec2d660	add assertions for synth_microchip tests	2024-07-04 15:45:44 -04:00

Renamed from tests/arch/microchip/simple_ram/simple_ram.ys (Browse further)