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Author	SHA1	Message	Date
Eddie Hung	52fbaeca07	tests: update fsm.ys resource count Suspect it is to do with map/set ordering in techmap; should be fixed by #1862?	2020-07-04 19:45:10 +02:00
Dan Ravensloft	8b4eb78849	intel_alm: fix DFFE matching	2020-06-11 19:55:51 +02:00
Dan Ravensloft	2e37e62e6b	synth_intel_alm: alternative synthesis for Intel FPGAs By operating at a layer of abstraction over the rather clumsy Intel primitives, we can avoid special hacks like `dffinit -highlow` in favour of simple techmapping. This also makes the primitives much easier to manipulate, and more descriptive (no more cyclonev_lcell_comb to mean anything from a LUT2 to a LUT6).	2020-04-15 11:40:41 +02:00

Author

SHA1

Message

Date

Eddie Hung

52fbaeca07

tests: update fsm.ys resource count

Suspect it is to do with map/set ordering in techmap; should
be fixed by #1862?

2020-07-04 19:45:10 +02:00

Dan Ravensloft

8b4eb78849

intel_alm: fix DFFE matching

2020-06-11 19:55:51 +02:00

Dan Ravensloft

2e37e62e6b

synth_intel_alm: alternative synthesis for Intel FPGAs

By operating at a layer of abstraction over the rather clumsy Intel primitives,
we can avoid special hacks like `dffinit -highlow` in favour of simple techmapping.

This also makes the primitives much easier to manipulate, and more descriptive
(no more cyclonev_lcell_comb to mean anything from a LUT2 to a LUT6).

2020-04-15 11:40:41 +02:00

3 commits