Alberto Gonzalez
209a123b97
glift: Add initial hierarchy support.
2020-07-01 19:51:47 +00:00
Alberto Gonzalez
20ad371724
glift: Replace YS_OVERRIDE with override.
2020-07-01 19:51:47 +00:00
Alberto Gonzalez
8ec5929f97
glift: Add CODEOWNERS entry.
2020-07-01 19:51:47 +00:00
Alberto Gonzalez
91c20fca72
glift: Add -simple-cost-model option
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Rather than assigning specific weights to specific versions of taint tracking logic and summing the weights of all GLIFT cells, sum the following values for each GLIFT cell:
- 0 if the associated hole/$anyconst cell value is non-zero, i.e. reduced-precision taint tracking logic is chosen at this cell
- 1 if the associated hole/$anyconst cell value is zero, i.e. the full-precision taint tracking logic is chosen at this cell
This simplified cost modeling reduces the potential for the QBF-SAT solver to minimize taint tracking logic area but significantly simplifies the QBF-SAT problem.
2020-07-01 19:51:47 +00:00
Alberto Gonzalez
c26a8d1ee0
glift: Use qbfsat -O2 instead of manually calling abc.
2020-07-01 19:51:47 +00:00
Alberto Gonzalez
26bd686259
glift: Add -instrument-more option to add 4 more versions of taint tracking logic. Also refactor a bit and update help text.
2020-07-01 19:51:46 +00:00
Alberto Gonzalez
bc207d5426
glift: Change command names to better represent their functions.
2020-07-01 19:51:46 +00:00
Alberto Gonzalez
ddfb9f08e2
glift: Add -create-imprecise command, rename other commands, and re-work the help text.
2020-07-01 19:51:46 +00:00
Alberto Gonzalez
ca3844d44e
glift: Add examples, including a number of benchmarks used in some academic works.
2020-07-01 19:51:46 +00:00
Alberto Gonzalez
72cebef279
glift: Add replacement scoring and area minimization option.
2020-07-01 19:51:46 +00:00
Alberto Gonzalez
c36440a7ee
glift: Remove outputs by default; add -keep-outputs option; properly reset internal state between calls.
2020-07-01 19:51:46 +00:00
Alberto Gonzalez
19dafcd4f1
glift: Initial implementation of the -sketchify option.
2020-07-01 19:51:46 +00:00
Alberto Gonzalez
09848b3b9f
glift: Initial implementation of GLIFT model construction.
2020-07-01 19:51:45 +00:00
Alberto Gonzalez
5f45fe51ea
glift: Add skeleton for glift command.
2020-07-01 19:51:45 +00:00
clairexen
7450ee7f8a
Merge pull request #2203 from antmicro/fix-grammar
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Signed and macro grammar update
2020-07-01 16:41:32 +02:00
clairexen
8ce4f8790e
Merge pull request #2179 from splhack/static-cast
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Support SystemVerilog Static Cast
2020-07-01 16:40:20 +02:00
clairexen
b1707407a0
Merge pull request #2138 from boqwxp/qbfsat-oflag
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qbfsat: Add `-O[012]` options to control pre-solving simplification with ABC
2020-07-01 16:35:27 +02:00
clairexen
2b0f6e24e2
Merge pull request #2206 from boqwxp/qbfsat-fix-name-specialization
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qbfsat: Fix name-based hole specialization
2020-07-01 16:34:32 +02:00
Marcelina Kościelnicka
6b42819a37
dfflegalize: Add tests.
2020-07-01 01:57:15 +02:00
Marcelina Kościelnicka
e3564b4502
Add dfflegalize pass.
2020-07-01 01:57:15 +02:00
Marcelina Kościelnicka
7c91f13f51
fmcombine: use the master ff cell type list
2020-06-30 21:07:17 +02:00
Marcelina Kościelnicka
77b15dd8e9
opt_merge: use the master FF type list
2020-06-30 20:57:35 +02:00
clairexen
9d658a1970
Merge pull request #2136 from zachjs/master
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Allow constant function calls in for loops and generate if and case
2020-06-30 17:38:49 +02:00
clairexen
3fb5b4fd8a
Merge pull request #2199 from YosysHQ/mmicko/sim_memory
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sim - error when memrd and memwr detected
2020-06-30 17:12:51 +02:00
clairexen
275cee71f6
Merge pull request #2201 from YosysHQ/fix_test_cell_ilang
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Use ID macro to fix assertion
2020-06-30 17:11:13 +02:00
clairexen
79d81b7f4f
Merge pull request #2209 from YosysHQ/verific_update
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Update verific API version check
2020-06-30 17:05:51 +02:00
Marcelina Kościelnicka
817ae04ee0
simcells: Fix reset polarity for $_DLATCH_???_ cells.
2020-06-30 15:32:06 +02:00
Miodrag Milanovic
561890c4e8
Update verific API version check
2020-06-30 12:13:13 +02:00
Alberto Gonzalez
83c595aaac
qbfsat: Add -O[012] options to control pre-solving simplification with ABC.
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Thanks to @mwk for the gate mapping part of the ABC scripts.
Co-Authored-By: Marcelina Kościelnicka <mwk@0x04.net>
2020-06-30 06:44:17 +00:00
Alberto Gonzalez
f544a2cc84
qbfsat: Fix name-based hole specialization.
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Look for unique connections in the containing module with the $anyconst port Y SigBit on the RHS and use those. If no such connection is found, fall back to using the name of the $anyconst port Y SigBit.
2020-06-30 01:53:21 +00:00
whitequark
f7fdd99e45
Merge pull request #2205 from whitequark/fix-2204
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techmap: don't drop attributes on replaced cells
2020-06-30 00:08:08 +00:00
whitequark
a97c13f0ca
techmap: don't drop attributes on replaced cells.
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This was introduced in 76c4ee4ea5Fixes #2204 .
2020-06-29 23:14:13 +00:00
Zachary Snow
27cec16cda
Allow constant function calls in for loops and generate if and case
2020-06-29 16:06:17 -06:00
Miodrag Milanović
4160acc0b1
Merge pull request #2200 from YosysHQ/mmicko/fix_expose
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expose pass fix
2020-06-29 15:16:29 +02:00
Miodrag Milanovic
405b4e97a1
Give error that options are exclusive
2020-06-29 14:45:49 +02:00
Miodrag Milanovic
0545a042f3
cleanup
2020-06-29 14:42:48 +02:00
whitequark
7860fb628f
Merge pull request #2197 from Xiretza/test_cell-shifts
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test_cell: don't generate directional shifts with \B_SIGNED=1
2020-06-29 12:34:09 +00:00
Miodrag Milanovic
5aae936044
Use ID macro to fix assertion
2020-06-29 13:18:13 +02:00
Miodrag Milanovic
87717d67d1
expose pass fix
2020-06-29 11:56:43 +02:00
Miodrag Milanovic
48b6d3272c
sim - error when memrd and memwr detected
2020-06-29 10:33:39 +02:00
Xiretza
e2cfe57edd
test_cell: don't generate directional shifts with \B_SIGNED=1
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This was made an explicit error in e97e33d
2020-06-28 21:30:16 +02:00
Marcelina Kościelnicka
2db270cbc7
Add latches to the manual.
2020-06-26 23:27:14 +02:00
Marcelina Kościelnicka
80a0cf9bb8
Add a few more gate types to the manual.
2020-06-26 23:27:14 +02:00
Miodrag Milanovic
b822beb1b2
Fix crash in verific frontend
2020-06-26 20:11:01 +02:00
Kamil Rakoczy
76a34dc5f3
Add signed/unsigned tests
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Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
2020-06-26 15:38:20 +02:00
Lukasz Dalek
6f9be939bd
Parse macro call attached semicolon as empty expression
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Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
2020-06-26 15:38:20 +02:00
Lukasz Dalek
7cb56f34b0
Fix integer signing grammar
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This commit fixes signed/unsigned grammar in parameters as defined in SV
LRM A2.2.1. Example of correct parameters:
parameter integer signed i = 0;
parameter integer unsigned i = 0;
Example of incorrect parameters:
parameter signed integer i = 0;
parameter unsigned integer i = 0;
Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
2020-06-26 15:35:56 +02:00
whitequark
3840cfc016
Merge pull request #2193 from whitequark/cxxrtl-help-text
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cxxrtl: update help text
2020-06-26 08:48:15 +00:00
whitequark
a746c4b605
cxxrtl: update help text.
2020-06-26 08:30:44 +00:00
whitequark
12c016ebdc
Merge pull request #2188 from antmicro/missing-operators
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Add logic-assignments operators
2020-06-26 07:30:27 +00:00
