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Author SHA1 Message Date
Zachary Snow
f55fbb5803 verilog: indirect AST_CONCAT and AST_TO_UNSIGNED port connections 
- AST_CONCAT and AST_TO_UNSIGNED are always unsigned, but may generate
  RTLIL that exclusively reference a signed wire.
- AST_CONCAT may also contain a memory write.
 2025-09-23 15:04:09 +02:00