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Code Activity
7936 commits 120 branches 56 tags 56 MiB
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7 commits

Author SHA1 Message Date
Diego H
f3f59910eb Removing fixed attribute value to !ramstyle rules 2019-12-15 23:51:58 -06:00
Diego H
b35559fc33 Merging attribute rules into a single match block; Adding tests 2019-12-15 23:33:09 -06:00
Diego H
266993408a Refactoring memory attribute matching based on IEEE 1364.1 and Tool specific 2019-12-13 15:43:24 -06:00
Diego H
751a18d7e9 Fixing citation in xc7_xcu_brams.txt file. Fixing RAMB36E1 test. 2019-12-12 17:32:58 -06:00
Diego H
937ec1ee78 Updating RAMB36E1 thresholds. Adding test for both RAMB18E1/RAMB36E1 2019-12-12 13:50:36 -06:00
Diego H
3a5a65829c Adjusting Vivado's BRAM min bits threshold for RAMB18E1 2019-11-27 12:05:04 -06:00
David Shah
6769d31ddb xilinx: Add support for UltraScale[+] BRAM mapping 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-23 11:47:37 +01:00
Renamed from techlibs/xilinx/xc7_brams.txt (Browse further)