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31 commits

Author SHA1 Message Date
Emil J. Tywoniak
642e041f77 const2ast: fix for consistency with previous diagnostics behavior 2025-08-11 13:34:10 +02:00
Emil J. Tywoniak
27899180a3 fixup! fixup! ast, read_verilog: unify location types, reduce filename copying 2025-08-11 13:34:10 +02:00
Emil J. Tywoniak
8bf750ecbb neater errors, lost in the sauce of source 2025-08-11 13:34:10 +02:00
Emil J. Tywoniak
b3bf588966 ast, read_verilog: refactoring 2025-08-11 13:34:10 +02:00
Emil J. Tywoniak
c8e0ac0c61 ast, read_verilog: ownership in AST, use C++ styles for parser and lexer 2025-08-11 13:34:10 +02:00
Marcelina Kościelnicka
801ecc0e1d verilog: Squash a memory leak. 
That was added in ecc22f7fed
 2021-06-14 17:07:41 +02:00
Claire Xenia Wolf
72787f52fc Fixing old e-mail addresses and deadnames 
s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi;
s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi;
s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi;
s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi;
s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;
 2021-06-08 00:39:36 +02:00
Eddie Hung
22bf22fab4 frontend: cleanup to use more ID::*, more dict<> instead of map<> 2020-05-04 10:48:37 -07:00
N. Engelhardt
d5e2061687
Merge pull request #1811 from PeterCrozier/typedef_scope 
Support module/package/interface/block scope for typedef names.
 2020-03-30 13:55:39 +02:00
Rupert Swarbrick
044ca9dde4 Add support for SystemVerilog-style `define to Verilog frontend 
This patch should support things like

  `define foo(a, b = 3, c)   a+b+c

  `foo(1, ,2)

which will evaluate to 1+3+2. It also spots mistakes like

  `foo(1)

(the 3rd argument doesn't have a default value, so a call site is
required to set it).

Most of the patch is a simple parser for the format in preproc.cc, but
I've also taken the opportunity to wrap up the "name -> definition"
map in a type, rather than use multiple std::map's.

Since this type needs to be visible to code that touches defines, I've
pulled it (and the frontend_verilog_preproc declaration) out into a
new file at frontends/verilog/preproc.h and included that where
necessary.

Finally, the patch adds a few tests in tests/various to check that we
are parsing everything correctly.
 2020-03-27 16:08:26 +00:00
Peter Crozier
ecc22f7fed Support module/package/interface/block scope for typedef names. 2020-03-23 20:07:22 +00:00
Peter
14f32028ec Parser changes to support typedef. 2020-03-22 18:20:46 -07:00
Alberto Gonzalez
f0afd65035
Closes #1717. Add more precise Verilog source location information to AST and RTLIL nodes. 2020-02-23 07:22:26 +00:00
Clifford Wolf
3cc95fb4be Add specify parser 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-23 21:36:59 +02:00
Clifford Wolf
fb7f02be55 New behavior for front-end handling of whiteboxes 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-20 22:24:50 +02:00
Clifford Wolf
f4abc21d8a Add "whitebox" attribute, add "read_verilog -wb" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-18 17:45:47 +02:00
Clifford Wolf
8fde05dfa5 Add "read_verilog -noassert -noassume -assert-assumes" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-09-24 20:51:16 +02:00
Clifford Wolf
a926a6afc2 Remember global declarations and defines accross read_verilog calls 2016-11-15 12:42:43 +01:00
Clifford Wolf
1276c87a56 Added read_verilog -norestrict -assume-asserts 2016-08-26 23:35:27 +02:00
Clifford Wolf
9aae1d1e8f No tristate warning message for "read_verilog -lib" 2016-07-23 11:56:53 +02:00
Clifford Wolf
6c84341f22 Fixed trailing whitespaces 2015-07-02 11:14:30 +02:00
Clifford Wolf
1f1deda888 Added non-std verilog assume() statement 2015-02-26 18:47:39 +01:00
Clifford Wolf
87333f3ae2 Added warning for use of 'z' constants in HDL 2014-11-14 19:59:50 +01:00
Clifford Wolf
19cff41eb4 Changed frontend-api from FILE to std::istream 2014-08-23 15:03:55 +02:00
Clifford Wolf
1cb25c05b3 Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace 2014-07-31 13:19:47 +02:00
Clifford Wolf
482d9208aa Added read_verilog -sv options, added support for bit, logic, 
allways_ff, always_comb, and always_latch
 2014-06-12 11:54:20 +02:00
Clifford Wolf
02e6f2c5be Added Verilog support for "`default_nettype none" 2014-02-17 14:28:52 +01:00
Clifford Wolf
e4429c480e Enable {* .. *} feature per default (removes dependency to REJECT feature in flex) 2013-11-22 12:46:02 +01:00
Johann Glaser
a99c224157 Added support for include directories with the new '-I' argument of the 
'read_verilog' command
 2013-08-20 15:48:16 +02:00
Johann Glaser
10a195c0a1 added option '-Dname[=definition]' to command 'read_verilog' 2013-05-19 17:07:52 +02:00
Clifford Wolf
7764d0ba1d initial import 2013-01-05 11:13:26 +01:00