Eddie Hung
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eb21bf3651
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log_warning_noprefix -> log_warning as per review
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2019-05-03 20:53:25 +02:00 |
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Eddie Hung
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a27b42e975
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WIP -chparam support for hierarchy when verific
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2019-05-03 20:53:25 +02:00 |
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Clifford Wolf
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373b236108
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Merge pull request #969 from YosysHQ/clifford/pmgenstuff
Improve pmgen, Add "peepopt" pass with shift-mul pattern
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2019-05-03 20:39:50 +02:00 |
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Clifford Wolf
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f170fb6383
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Merge pull request #984 from YosysHQ/eddie/fix_982
dffinit to do nothing when (* init *) value is 1'bx
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2019-05-03 20:34:32 +02:00 |
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Eddie Hung
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e08df0c739
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If init is 1'bx, do not add to dict as per @cliffordwolf
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2019-05-03 08:06:16 -07:00 |
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Eddie Hung
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fc349de033
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Revert "dffinit -noreinit to silently continue when init value is 1'bx"
This reverts commit aa081f83c7.
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2019-05-03 08:05:37 -07:00 |
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Clifford Wolf
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42190207b4
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Improve opt_expr and opt_clean handling of (partially) undriven and/or unused wires, fixes #981
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-05-03 14:25:01 +02:00 |
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Clifford Wolf
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5c2c0b4bb2
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Further improve unused-detection for opt_clean driver-driver conflict warning
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-05-03 09:22:26 +02:00 |
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Clifford Wolf
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f12e1155f1
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Improve unused-detection for opt_clean driver-driver conflict warning
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-05-03 09:12:10 +02:00 |
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Clifford Wolf
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2b29aa5c86
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Update pmgen documentation
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-05-03 08:35:45 +02:00 |
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Clifford Wolf
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e8c5afcb84
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Fix typo
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-05-03 08:25:30 +02:00 |
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Eddie Hung
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aa081f83c7
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dffinit -noreinit to silently continue when init value is 1'bx
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2019-05-02 17:40:39 -07:00 |
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Eddie Hung
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8829cba901
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Merge remote-tracking branch 'origin/clifford/pmgenstuff' into xc7mux
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2019-05-02 11:25:34 -07:00 |
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Eddie Hung
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5cd19b52da
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Merge remote-tracking branch 'origin/master' into xc7mux
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2019-05-02 10:44:59 -07:00 |
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Eddie Hung
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f86d153cef
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Merge branch 'master' of github.com:YosysHQ/yosys
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2019-05-01 16:26:43 -07:00 |
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Clifford Wolf
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521663f09e
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Add missing enable_undef to "sat -tempinduct-def", fixes #883
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-05-02 00:03:31 +02:00 |
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Clifford Wolf
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93b7fd7744
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Fix floating point exception in qwp, fixes #923
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-05-01 15:06:46 +02:00 |
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Clifford Wolf
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a30b99e66e
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Silently resolve completely unused cell-vs-const driver-driver conflicts
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-05-01 09:29:34 +02:00 |
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Clifford Wolf
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32ff37bb5a
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Fix segfault in wreduce
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-04-30 22:20:45 +02:00 |
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Clifford Wolf
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a27eeff573
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Merge pull request #966 from YosysHQ/clifford/fix956
Drive dangling wires with init attr with their init value
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2019-04-30 18:08:41 +02:00 |
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Clifford Wolf
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9d117eba9d
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Add handling of init attributes in "opt_expr -undriven"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-04-30 14:46:12 +02:00 |
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Clifford Wolf
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b515fd2d25
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Add peepopt_muldiv, fixes #930
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-04-30 11:25:15 +02:00 |
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Clifford Wolf
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4306bebe58
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pmgen progress
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-04-30 10:51:51 +02:00 |
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Clifford Wolf
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bb4f3642de
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Some pmgen reorg, rename peepopt.pmg to peepopt_shiftmul.pmg
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-04-30 08:04:22 +02:00 |
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Clifford Wolf
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58238da133
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Progress in shiftmul peepopt pattern
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-04-30 07:59:39 +02:00 |
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Clifford Wolf
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ea547bcaa3
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Add "peepopt" skeleton
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-04-29 13:38:56 +02:00 |
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Clifford Wolf
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9f792c599d
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Add pmgen support for multiple patterns in one matcher
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-04-29 13:02:05 +02:00 |
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Clifford Wolf
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32881a989c
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Support multiple pmg files (right now just concatenated together)
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-04-29 12:09:02 +02:00 |
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Clifford Wolf
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754b1ee4b3
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Drive dangling wires with init attr with their init value, fixes #956
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2019-04-29 08:44:53 +02:00 |
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Eddie Hung
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acafcdc94d
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Copy with 1'bx padding in $shiftx
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2019-04-28 13:04:34 -07:00 |
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Eddie Hung
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dcc8a13e48
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Revert "Merge branch 'eddie/split_shiftx' into xc7mux"
This reverts commit 3042d58330, reversing
changes made to feff976454.
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2019-04-26 15:32:02 -07:00 |
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Eddie Hung
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159e7cc298
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Add -undef option to equiv_opt, passed to equiv_induct
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2019-04-26 11:16:48 -07:00 |
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Eddie Hung
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4473fd1502
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Add -undef option to equiv_opt, passed to equiv_induct
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2019-04-26 11:14:33 -07:00 |
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Eddie Hung
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976d8030dc
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Actually use pm.st.shiftxB
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2019-04-25 19:59:33 -07:00 |
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Eddie Hung
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fb4348f840
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Fix for when B_WIDTH has trailing zeroes
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2019-04-25 19:38:19 -07:00 |
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Eddie Hung
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880652283c
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Merge remote-tracking branch 'origin/eddie/split_shiftx' into xc7mux
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2019-04-25 18:52:20 -07:00 |
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Eddie Hung
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ece2c49e92
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In order to indicate a failed pattern, blacklist?
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2019-04-25 18:39:13 -07:00 |
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Eddie Hung
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af3c374a35
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Elaborate on help message
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2019-04-25 17:35:39 -07:00 |
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Eddie Hung
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3042d58330
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Merge branch 'eddie/split_shiftx' into xc7mux
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2019-04-25 17:31:27 -07:00 |
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Eddie Hung
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ccd0729456
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Add split_shiftx command
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2019-04-25 17:23:59 -07:00 |
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Eddie Hung
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8d00b9ef7e
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Make pmgen support files more generic
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2019-04-25 17:23:46 -07:00 |
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Eddie Hung
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408161ea3a
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Misspelling
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2019-04-25 16:46:13 -07:00 |
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Eddie Hung
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d9c915042a
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Move clean from aigerparse to abc9
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2019-04-23 13:42:35 -07:00 |
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Clifford Wolf
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71c38d9de5
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Add $specrule cells for $setup/$hold/$skew specify rules
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-04-23 21:36:59 +02:00 |
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Clifford Wolf
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634482380c
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Preserve $specify[23] cells
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-04-23 21:36:59 +02:00 |
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Clifford Wolf
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c84cdc711c
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Remove some left-over log_dump()
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-04-23 17:55:41 +02:00 |
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Eddie Hung
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4df4a97ffa
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Merge branch 'xaig' of github.com:YosysHQ/yosys into xaig
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2019-04-22 18:20:39 -07:00 |
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Eddie Hung
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0bd2bfa737
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Merge remote-tracking branch 'origin/master' into xaig
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2019-04-22 18:15:28 -07:00 |
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Eddie Hung
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5f30a8795d
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Tidy up
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2019-04-22 17:47:05 -07:00 |
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Eddie Hung
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d9daf09cf3
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Merge pull request #914 from YosysHQ/xc7srl
synth_xilinx to now infer SRL16E/SRLC32E
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2019-04-22 13:31:30 -07:00 |
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