5714 commits

This branch

This branch

All branches

Author	SHA1	Message	Date
Clifford Wolf	64925b4e8f	Improve $specrule interface ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-04-23 22:57:10 +02:00
Eddie Hung	d9c915042a	Move clean from aigerparse to abc9	2019-04-23 13:42:35 -07:00
Eddie Hung	91c3afcab7	Use nonblocking	2019-04-23 13:42:06 -07:00
Clifford Wolf	4575e4ad86	Improve $specrule interface ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-04-23 22:18:04 +02:00
Clifford Wolf	71c38d9de5	Add $specrule cells for $setup/$hold/$skew specify rules ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-04-23 21:36:59 +02:00
Clifford Wolf	634482380c	Preserve $specify[23] cells ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-04-23 21:36:59 +02:00
Clifford Wolf	012c6af088	Allow $specify[23] cells in blackbox modules ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-04-23 21:36:59 +02:00
Clifford Wolf	e807e88b60	Rename T_{RISE,FALL}_AVG to T_{RISE,FALL}_TYP to better match verilog std nomenclature ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-04-23 21:36:59 +02:00
Clifford Wolf	846eb5ea98	Add $specify2/$specify3 support to write_verilog ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-04-23 21:36:59 +02:00
Clifford Wolf	0bf9d0087c	Add support for $assert/$assume/$cover to write_verilog ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-04-23 21:36:59 +02:00
Clifford Wolf	aec2475a9d	Add CellTypes support for $specify2 and $specify3 ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-04-23 21:36:59 +02:00
Clifford Wolf	e1d73e03d3	Add InternalCellChecker support for $specify2 and $specify3 ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-04-23 21:36:59 +02:00
Clifford Wolf	b232e027bf	Checking and fixing specify cells in genRTLIL ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-04-23 21:36:59 +02:00
Clifford Wolf	41b843c27b	Un-break default specify parser ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-04-23 21:36:59 +02:00
Clifford Wolf	3cc95fb4be	Add specify parser ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-04-23 21:36:59 +02:00
Clifford Wolf	a7e11261bd	Add $specify2 and $specify3 cells to simlib ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-04-23 21:36:59 +02:00
Clifford Wolf	b2020ab44f	Merge pull request #957 from YosysHQ/oai4fix ... Fixes for OAI4 cell implementation	2019-04-23 19:59:39 +02:00
David Shah	742c2f245d	Fixes for OAI4 cell implementation ... Fixes #955 and the underlying issue in #954 Signed-off-by: David Shah <dave@ds0.me>	2019-04-23 17:54:00 +01:00
Eddie Hung	c6156f3118	Format some names using inline code	2019-04-23 09:01:10 -07:00
Eddie Hung	f66792c43a	Fix spelling	2019-04-23 08:58:34 -07:00
Clifford Wolf	c84cdc711c	Remove some left-over log_dump() ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-04-23 17:55:41 +02:00
Eddie Hung	4df4a97ffa	Merge branch 'xaig' of github.com:YosysHQ/yosys into xaig	2019-04-22 18:20:39 -07:00
Eddie Hung	0bd2bfa737	Merge remote-tracking branch 'origin/master' into xaig	2019-04-22 18:15:28 -07:00
Eddie Hung	60026842b2	Tweak	2019-04-22 17:59:56 -07:00
Eddie Hung	26e461f47d	Fix for A_WIDTH == 2 but B_WIDTH==3	2019-04-22 17:58:28 -07:00
Eddie Hung	5f30a8795d	Tidy up	2019-04-22 17:47:05 -07:00
Eddie Hung	8f30019b68	Revert "Temporarily remove 'r' extension" ... This reverts commit eaf3c24772.	2019-04-22 17:41:21 -07:00
Eddie Hung	1fa2c36fbd	Trim A_WIDTH by Y_WIDTH-1	2019-04-22 17:14:11 -07:00
Eddie Hung	69863f7698	Add comment	2019-04-22 16:58:44 -07:00
Eddie Hung	61161faefc	Fix for mux_case_* mappings	2019-04-22 16:56:18 -07:00
Eddie Hung	ac1e13819e	Fix for non-pow2 width muxes	2019-04-22 14:26:13 -07:00
Eddie Hung	d9daf09cf3	Merge pull request #914 from YosysHQ/xc7srl ... synth_xilinx to now infer SRL16E/SRLC32E	2019-04-22 13:31:30 -07:00
Eddie Hung	75b96b1aff	Add synth_xilinx -nomux option	2019-04-22 12:36:15 -07:00
Eddie Hung	79fb291dbe	Cleanup, call pmux2shiftx even without -nosrl	2019-04-22 12:14:37 -07:00
Eddie Hung	4cfef7897f	Merge branch 'xaig' into xc7mux	2019-04-22 11:58:59 -07:00
Eddie Hung	eaf3c24772	Temporarily remove 'r' extension	2019-04-22 11:54:19 -07:00
Eddie Hung	4486a98fd5	Merge remote-tracking branch 'origin/xc7srl' into xc7mux	2019-04-22 11:45:49 -07:00
Eddie Hung	ec88129a5c	Update help message	2019-04-22 11:38:23 -07:00
Eddie Hung	b780c0a7de	Allow POs to be PIs in XAIG	2019-04-22 11:22:29 -07:00
Eddie Hung	2c6358ea25	Remove kernel/cost.cc since master has refactored it	2019-04-22 11:21:17 -07:00
Eddie Hung	4883391b63	Merge remote-tracking branch 'origin/master' into xaig	2019-04-22 11:19:52 -07:00
Clifford Wolf	bc98a463a4	Merge pull request #952 from YosysHQ/clifford/fix370 ... Determine correct signedness and expression width in for-loop unrolling	2019-04-22 20:10:46 +02:00
Clifford Wolf	8ed4a53d99	Merge pull request #951 from YosysHQ/clifford/logdebug ... Add log_debug() framework	2019-04-22 20:09:51 +02:00
Clifford Wolf	1d538ff1ec	Merge pull request #949 from YosysHQ/clifford/pmux2shimprove ... Add full_pmux feature to pmux2shiftx	2019-04-22 20:01:43 +02:00
Clifford Wolf	3be5aac52c	Merge pull request #953 from YosysHQ/clifford/fix948 ... Add support for zero-width signals to Verilog back-end	2019-04-22 20:01:09 +02:00
Eddie Hung	0e76718720	Move 'shregmap -tech xilinx' into map_cells	2019-04-22 10:45:39 -07:00
Clifford Wolf	0e0c80fac8	Add support for zero-width signals to Verilog back-end, fixes #948 ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-04-22 19:44:42 +02:00
Eddie Hung	e300b1922c	Merge remote-tracking branch 'origin/master' into xc7srl	2019-04-22 10:36:27 -07:00
Clifford Wolf	4ad0ea5c3c	Determine correct signedness and expression width in for loop unrolling, fixes #370 ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-04-22 18:19:02 +02:00
Clifford Wolf	e158ea2097	Add log_debug() framework ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-04-22 17:25:52 +02:00