mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-10-31 11:42:30 +00:00
Code Activity
12128 commits 122 branches 59 tags 73 MiB
Commit graph

12128 commits

This branch
This branch
All branches
Author SHA1 Message Date
github-actions[bot]
224c6f8664 Bump version 2021-11-10 00:54:39 +00:00
Kamil Rakoczy
f4f5acf396 genrtlil: Fix displaying debug info in packages 
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
 2021-11-10 01:31:39 +01:00
Marcelina Kościelnicka
15b0d717ed iopadmap: Add native support for negative-polarity output enable. 2021-11-09 15:40:16 +01:00
github-actions[bot]
4871d8f199 Bump version 2021-11-09 00:53:27 +00:00
Miodrag Milanović
cd71d260ea
Update CODEOWNERS 2021-11-08 16:59:45 +01:00
Miodrag Milanović
cd3f3d5df0
Limit macOS GH actions 2021-11-08 16:56:24 +01:00
github-actions[bot]
d39d4e11d2 Bump version 2021-11-08 00:53:20 +00:00
Pepijn de Vos
4bf8deacbb
synth_gowin: move splitnets to after iopadmap (#2435) 2021-11-07 18:00:18 +01:00
Gabriel Somlo
9a413803eb manual: fix pdflatex inputenc undefined char error 
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
 2021-11-07 03:05:03 +01:00
Pepijn de Vos
a3eec687e0 Remove noalu from synth_gowin json output as Apicula now supports it 2021-11-07 03:04:21 +01:00
github-actions[bot]
781cf13abd Bump version 2021-11-07 00:54:38 +00:00
Pepijn de Vos
0c7461fe5e
gowin: widelut support (#3042) 2021-11-06 16:09:30 +01:00
github-actions[bot]
8f08908d8d Bump version 2021-11-06 00:51:08 +00:00
Miodrag Milanovic
a28ee81be0 Next dev cycle 2021-11-05 12:52:24 +01:00
Miodrag Milanovic
360fed8e4d Release version 0.11 2021-11-05 12:47:38 +01:00
Miodrag Milanovic
18bcf820b3 Must use latest flex to generate c++17 compatible code 2021-11-05 11:41:51 +01:00
Miodrag Milanovic
d5de2a0cdb Make it work on all 2021-11-05 10:51:58 +01:00
Miodrag Milanovic
cbb6887ac8 Correct way of setting maybe_unsused on labels 2021-11-05 10:36:15 +01:00
Miodrag Milanovic
051b234df6 Add missing changelog item 2021-11-05 10:08:50 +01:00
Miodrag Milanovic
598f51c6a1 Update command reference 2021-11-05 10:04:15 +01:00
Miodrag Milanović
5a5244a12e
Merge pull request #3067 from YosysHQ/aki/ci_update 
Update the Linux and macOS CI jobs
 2021-11-05 09:58:35 +01:00
Miodrag Milanovic
d67eb0eb1c Removed semicolon from macro 2021-11-05 09:57:37 +01:00
github-actions[bot]
11e58d5415 Bump version 2021-11-03 00:52:24 +00:00
Marcelina Kościelnicka
f346868ccc flatten: Keep sigmap around between flatten_cell invocations. 
Fixes #3064.
 2021-11-02 13:18:15 +01:00
github-actions[bot]
9cb5092ad1 Bump version 2021-11-02 00:56:31 +00:00
Claire Xen
5b834d3aff
Merge pull request #3068 from YosysHQ/claire/verific_cfg 
Add "verific -cfg" command
 2021-11-01 12:53:47 +01:00
Claire Xenia Wolf
2ea757da51 Add "verific -cfg" command 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2021-11-01 10:41:51 +01:00
github-actions[bot]
97fce665c7 Bump version 2021-11-01 01:05:04 +00:00
Aki Van Ness
e1cfd37384
ci: removed the old test.yml workflow, as it was replaced by test-linux.yml and test-macos.yml 2021-10-31 20:07:43 -04:00
Aki Van Ness
1e7ba922e5
ci: expanded the macOS tests suite to cover more compilers and C++ versions 2021-10-31 20:07:43 -04:00
Aki Van Ness
ff31af6d72
ci: expanded the Linux test suite to cover more compilers and C++ versions 2021-10-31 20:07:43 -04:00
Aki Van Ness
ad81cff823
Changed the Makefile to have an explicit CXXSTD parameter which allows for the setting of other C++ standards, the default is c++11 2021-10-31 20:07:30 -04:00
Claire Xen
dd06d23649
Merge pull request #3066 from YosysHQ/claire/verific_gclk 
Fix verific gclk handling for async-load FFs
 2021-10-31 18:04:54 +01:00
Claire Xenia Wolf
83118bfb9e Fix verific gclk handling for async-load FFs 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2021-10-31 17:12:29 +01:00
github-actions[bot]
dcb7096b5a Bump version 2021-10-30 00:51:07 +00:00
Miodrag Milanovic
c0edfa8788 Add missing items in CHANGELOG 2021-10-29 13:31:41 +02:00
Miodrag Milanovic
55f07fe56f Update command reference part of manual 2021-10-29 13:10:50 +02:00
github-actions[bot]
5f00bf2d7d Bump version 2021-10-28 00:52:35 +00:00
Miodrag Milanović
19c2d6e15d
Merge pull request #3063 from YosysHQ/micko/verific_aldff 
Enable async load dff emit by default in Verific
 2021-10-27 17:20:31 +02:00
Marcelina Kościelnicka
e14302a3ea ecp5: Add support for mapping aldff. 2021-10-27 16:18:05 +02:00
Miodrag Milanovic
f7cc388bb5 Enable async load dff emit by default in Verific 2021-10-27 15:56:56 +02:00
Miodrag Milanovic
32673edfea Revert "Compile option for enabling async load verific support" 
This reverts commit b8624ad2ae.
 2021-10-27 15:55:43 +02:00
Marcelina Kościelnicka
8d881826eb proc_dff: Emit $aldff. 2021-10-27 14:14:24 +02:00
Marcelina Kościelnicka
0b31cb598e dfflegalize: Add tests for aldff lowering. 2021-10-27 14:14:01 +02:00
Marcelina Kościelnicka
54c79af64f dfflegalize: Add tests targetting aldff. 2021-10-27 14:14:01 +02:00
Marcelina Kościelnicka
0a0df8d38c dfflegalize: Refactor, add aldff support. 2021-10-27 14:14:01 +02:00
github-actions[bot]
bdf153d06c Bump version 2021-10-27 00:51:44 +00:00
Zachary Snow
e833c6a418 verilog: use derived module info to elaborate cell connections 
- Attempt to lookup a derived module if it potentially contains a port
  connection with elaboration ambiguities
- Mark the cell if module has not yet been derived
- This can be extended to implement automatic hierarchical port
  connections in a future change
 2021-10-25 18:25:50 -07:00
Rupert Swarbrick
bd16d01c0e Split out logic for reprocessing an AstModule 
This will enable other features to use same core logic for replacing an
existing AstModule with a newly elaborated version.
 2021-10-25 18:25:50 -07:00
github-actions[bot]
ee230f2bb9 Bump version 2021-10-26 00:51:59 +00:00